3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
11 #define MAX_HW_CFG_SIZE_V2 121 /* Max number of registers imx can set for v2 */
12 #define MAX_HW_CFG_SIZE_V1 60 /* Max number of registers imx can set for v1 */
13 #define APP_CODE_BARKER 0xB1
14 #define DCD_BARKER 0xB17219E9
16 #define HEADER_OFFSET 0x400
19 * NOTE: This file must be kept in sync with arch/arm/include/asm/\
20 * imx-common/imximage.cfg because tools/imximage.c can not
21 * cross-include headers from arch/arm/ and vice-versa.
23 #define CMD_DATA_STR "DATA"
24 #define FLASH_OFFSET_UNDEFINED 0xFFFFFFFF
25 #define FLASH_OFFSET_STANDARD 0x400
26 #define FLASH_OFFSET_NAND FLASH_OFFSET_STANDARD
27 #define FLASH_OFFSET_SD FLASH_OFFSET_STANDARD
28 #define FLASH_OFFSET_SPI FLASH_OFFSET_STANDARD
29 #define FLASH_OFFSET_ONENAND 0x100
30 #define FLASH_OFFSET_NOR 0x1000
31 #define FLASH_OFFSET_SATA FLASH_OFFSET_STANDARD
33 #define IVT_HEADER_TAG 0xD1
34 #define IVT_VERSION 0x40
35 #define DCD_HEADER_TAG 0xD2
36 #define DCD_COMMAND_TAG 0xCC
37 #define DCD_VERSION 0x40
38 #define DCD_COMMAND_PARAM 0x4
48 enum imximage_fld_types {
56 enum imximage_version {
57 IMXIMAGE_VER_INVALID = -1,
63 uint32_t type; /* Type of pointer (byte, halfword, word, wait/read) */
64 uint32_t addr; /* Address to write to */
65 uint32_t value; /* Data to write */
66 } dcd_type_addr_data_t;
69 uint32_t barker; /* Barker for sanity check */
70 uint32_t length; /* Device configuration length (without preamble) */
74 dcd_preamble_t preamble;
75 dcd_type_addr_data_t addr_data[MAX_HW_CFG_SIZE_V1];
79 uint32_t app_code_jump_vector;
80 uint32_t app_code_barker;
81 uint32_t app_code_csf;
83 uint32_t super_root_key;
85 uint32_t app_dest_ptr;
89 uint32_t length; /* Length of data to be read from flash */
93 flash_header_v1_t fhdr;
95 flash_cfg_parms_t ext_header;
107 } __attribute__((packed)) ivt_header_t;
113 } __attribute__((packed)) write_dcd_command_t;
117 write_dcd_command_t write_dcd_command;
118 dcd_addr_data_t addr_data[MAX_HW_CFG_SIZE_V2];
132 uint32_t boot_data_ptr;
139 flash_header_v2_t fhdr;
140 boot_data_t boot_data;
144 /* The header must be aligned to 4k on MX53 for NAND boot */
147 imx_header_v1_t hdr_v1;
148 imx_header_v2_t hdr_v2;
150 } __attribute__((aligned(4096)));
152 typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
153 char *name, int lineno,
154 int fld, uint32_t value,
157 typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
159 char *name, int lineno);
161 typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
162 uint32_t entry_point, uint32_t flash_offset);
164 #endif /* _IMXIMAGE_H_ */