1 // Copyright 2019 The Pigweed Authors
3 // Licensed under the Apache License, Version 2.0 (the "License"); you may not
4 // use this file except in compliance with the License. You may obtain a copy of
7 // https://www.apache.org/licenses/LICENSE-2.0
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
11 // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
12 // License for the specific language governing permissions and limitations under
18 #include "pw_preprocessor/compiler.h"
20 namespace pw::cpu_exception {
22 // This is dictated by ARMv7-M architecture. Do not change.
23 PW_PACKED(struct) CortexMExceptionRegisters {
29 uint32_t lr; // Link register.
30 uint32_t pc; // Program counter.
31 uint32_t psr; // Program status register.
34 // This is dictated by ARMv7-M architecture. Do not change.
35 PW_PACKED(struct) CortexMExceptionRegistersFpu {
56 // Bit in the PSR that indicates CPU added an extra word on the stack to
57 // align it during context save for an exception.
58 inline constexpr uint32_t kPsrExtraStackAlignBit = (1 << 9);
60 // This is dictated by this module, and shouldn't change often.
61 // Note that the order of entries in this struct is very important (as the
62 // values are populated in assembly).
64 // NOTE: Memory mapped registers are NOT restored upon fault return!
65 PW_PACKED(struct) CortexMExtraRegisters {
66 // Memory mapped registers.
78 // General purpose registers.
89 } // namespace pw::cpu_exception
91 PW_PACKED(struct) pw_cpu_exception_State {
92 pw::cpu_exception::CortexMExtraRegisters extended;
93 pw::cpu_exception::CortexMExceptionRegisters base;
94 // TODO(amontanez): FPU registers may or may not be here as well. Make the
95 // availability of the FPU registers a compile-time configuration when FPU
96 // register support is added.