1 /* basic set of prime tests between intel and nouveau */
4 1. share buffer from intel -> nouveau.
5 2. share buffer from nouveau -> intel
6 3. share intel->nouveau, map on both, write intel, read nouveau
7 4. share intel->nouveau, blit intel fill, readback on nouveau
8 test 1 + map buffer, read/write, map other size.
9 do some hw actions on the buffer
10 some illegal operations -
11 close prime fd try and map
13 TODO add some nouveau rendering tests
23 #include <sys/ioctl.h>
25 #include "ioctl_wrappers.h"
26 #include "intel_bufmgr.h"
29 #include "intel_batchbuffer.h"
30 #include "intel_chipset.h"
33 int intel_fd = -1, nouveau_fd = -1;
34 drm_intel_bufmgr *bufmgr;
35 struct nouveau_device *ndev;
36 struct nouveau_client *nclient;
38 struct intel_batchbuffer *intel_batch;
40 #define BO_SIZE (256*1024)
42 static int find_and_open_devices(void)
50 for (i = 0; i < 9; i++) {
53 sprintf(path, "/sys/class/drm/card%d/device/vendor", i);
57 fl = fopen(path, "r");
61 ret = fgets(vendor_id, 8, fl);
65 venid = strtoul(vendor_id, NULL, 16);
66 sprintf(path, "/dev/dri/card%d", i);
67 if (venid == 0x8086) {
68 intel_fd = open(path, O_RDWR);
71 } else if (venid == 0x10de) {
72 nouveau_fd = open(path, O_RDWR);
82 * allocate buffer on intel,
83 * set prime on buffer,
84 * retrive buffer from nouveau,
88 static void test_i915_nv_sharing(void)
90 drm_intel_bo *test_intel_bo;
92 struct nouveau_bo *nvbo;
94 test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
95 igt_assert(test_intel_bo);
97 drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
99 igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo) == 0);
102 nouveau_bo_ref(NULL, &nvbo);
103 drm_intel_bo_unreference(test_intel_bo);
108 * allocate buffer on nouveau
109 * set prime on buffer,
110 * retrive buffer from intel
114 static void test_nv_i915_sharing(void)
116 drm_intel_bo *test_intel_bo;
118 struct nouveau_bo *nvbo;
120 igt_assert(nouveau_bo_new(ndev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP,
121 0, BO_SIZE, NULL, &nvbo) == 0);
122 igt_assert(nouveau_bo_set_prime(nvbo, &prime_fd) == 0);
124 test_intel_bo = drm_intel_bo_gem_create_from_prime(bufmgr, prime_fd, BO_SIZE);
126 igt_assert(test_intel_bo);
128 nouveau_bo_ref(NULL, &nvbo);
129 drm_intel_bo_unreference(test_intel_bo);
133 * allocate intel, give to nouveau, map on nouveau
134 * write 0xdeadbeef, non-gtt map on intel, read
136 static void test_nv_write_i915_cpu_mmap_read(void)
138 drm_intel_bo *test_intel_bo;
140 struct nouveau_bo *nvbo = NULL;
143 test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
145 drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
147 igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo) == 0);
150 igt_assert(nouveau_bo_map(nvbo, NOUVEAU_BO_RDWR, nclient) == 0);
154 drm_intel_bo_map(test_intel_bo, 1);
155 ptr = test_intel_bo->virtual;
158 igt_assert(*ptr == 0xdeadbeef);
159 nouveau_bo_ref(NULL, &nvbo);
160 drm_intel_bo_unreference(test_intel_bo);
164 * allocate intel, give to nouveau, map on nouveau
165 * write 0xdeadbeef, gtt map on intel, read
167 static void test_nv_write_i915_gtt_mmap_read(void)
169 drm_intel_bo *test_intel_bo;
171 struct nouveau_bo *nvbo = NULL;
174 test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
176 drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
178 igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo) == 0);
180 igt_assert(nouveau_bo_map(nvbo, NOUVEAU_BO_RDWR, nclient) == 0);
184 drm_intel_gem_bo_map_gtt(test_intel_bo);
185 ptr = test_intel_bo->virtual;
188 igt_assert(*ptr == 0xdeadbeef);
190 nouveau_bo_ref(NULL, &nvbo);
191 drm_intel_bo_unreference(test_intel_bo);
194 /* test drm_intel_bo_map doesn't work properly,
195 this tries to map the backing shmem fd, which doesn't exist
197 static void test_i915_import_cpu_mmap(void)
199 drm_intel_bo *test_intel_bo;
201 struct nouveau_bo *nvbo;
204 igt_assert(nouveau_bo_new(ndev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP,
205 0, BO_SIZE, NULL, &nvbo) == 0);
206 igt_assert(nouveau_bo_set_prime(nvbo, &prime_fd) == 0);
207 test_intel_bo = drm_intel_bo_gem_create_from_prime(bufmgr, prime_fd, BO_SIZE);
209 igt_assert(test_intel_bo);
211 igt_assert(nouveau_bo_map(nvbo, NOUVEAU_BO_RDWR, nclient) == 0);
216 igt_assert(drm_intel_bo_map(test_intel_bo, 0) == 0);
217 igt_assert(test_intel_bo->virtual);
218 ptr = test_intel_bo->virtual;
220 igt_assert(*ptr == 0xdeadbeef);
221 nouveau_bo_ref(NULL, &nvbo);
222 drm_intel_bo_unreference(test_intel_bo);
225 /* test drm_intel_bo_map_gtt works properly,
226 this tries to map the backing shmem fd, which doesn't exist
228 static void test_i915_import_gtt_mmap(void)
230 drm_intel_bo *test_intel_bo;
232 struct nouveau_bo *nvbo;
235 igt_assert(nouveau_bo_new(ndev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP,
236 0, BO_SIZE, NULL, &nvbo) == 0);
237 igt_assert(nouveau_bo_set_prime(nvbo, &prime_fd) == 0);
239 test_intel_bo = drm_intel_bo_gem_create_from_prime(bufmgr, prime_fd, BO_SIZE);
241 igt_assert(test_intel_bo);
243 igt_assert(nouveau_bo_map(nvbo, NOUVEAU_BO_RDWR, nclient) == 0);
247 *(ptr + 1) = 0xa55a55;
249 igt_assert(drm_intel_gem_bo_map_gtt(test_intel_bo) == 0);
250 igt_assert(test_intel_bo->virtual);
251 ptr = test_intel_bo->virtual;
253 igt_assert(*ptr == 0xdeadbeef);
254 nouveau_bo_ref(NULL, &nvbo);
255 drm_intel_bo_unreference(test_intel_bo);
258 /* test 7 - import from nouveau into intel, test pread/pwrite fail */
259 static void test_i915_import_pread_pwrite(void)
261 drm_intel_bo *test_intel_bo;
263 struct nouveau_bo *nvbo;
267 igt_assert(nouveau_bo_new(ndev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP,
268 0, BO_SIZE, NULL, &nvbo) == 0);
269 igt_assert(nouveau_bo_set_prime(nvbo, &prime_fd) == 0);
271 test_intel_bo = drm_intel_bo_gem_create_from_prime(bufmgr, prime_fd, BO_SIZE);
273 igt_assert(test_intel_bo);
275 igt_assert(nouveau_bo_map(nvbo, NOUVEAU_BO_RDWR, nclient) == 0);
280 gem_read(intel_fd, test_intel_bo->handle, 0, buf, 256);
281 igt_assert(buf[0] == 0xdeadbeef);
284 gem_write(intel_fd, test_intel_bo->handle, 0, buf, 4);
286 igt_assert(*ptr == 0xabcdef55);
288 nouveau_bo_ref(NULL, &nvbo);
289 drm_intel_bo_unreference(test_intel_bo);
293 set_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
295 int size = width * height;
298 drm_intel_gem_bo_start_gtt_access(bo, true);
304 static drm_intel_bo *
305 create_bo(drm_intel_bufmgr *ibufmgr, uint32_t val, int width, int height)
309 bo = drm_intel_bo_alloc(ibufmgr, "bo", 4*width*height, 0);
312 /* gtt map doesn't have a write parameter, so just keep the mapping
313 * around (to avoid the set_domain with the gtt write domain set) and
314 * manually tell the kernel when we start access the gtt. */
315 drm_intel_gem_bo_map_gtt(bo);
317 set_bo(bo, val, width, height);
322 /* use intel hw to fill the BO with a blit from another BO,
323 then readback from the nouveau bo, check value is correct */
324 static void test_i915_blt_fill_nv_read(void)
326 drm_intel_bo *test_intel_bo, *src_bo;
328 struct nouveau_bo *nvbo = NULL;
331 src_bo = create_bo(bufmgr, 0xaa55aa55, 256, 1);
333 test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", BO_SIZE, 4096);
335 drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
337 igt_assert(nouveau_bo_prime_handle_ref(ndev, prime_fd, &nvbo) == 0);
340 intel_copy_bo(intel_batch, test_intel_bo, src_bo, BO_SIZE);
342 igt_assert(nouveau_bo_map(nvbo, NOUVEAU_BO_RDWR, nclient) == 0);
344 drm_intel_bo_map(test_intel_bo, 0);
347 igt_assert(*ptr == 0xaa55aa55);
348 nouveau_bo_ref(NULL, &nvbo);
349 drm_intel_bo_unreference(test_intel_bo);
352 /* test 8 use nouveau to do blit */
354 /* test 9 nouveau copy engine?? */
359 igt_assert(find_and_open_devices() == 0);
361 igt_require(nouveau_fd != -1);
362 igt_require(intel_fd != -1);
364 /* set up intel bufmgr */
365 bufmgr = drm_intel_bufmgr_gem_init(intel_fd, 4096);
367 /* Do not enable reuse, we share (almost) all buffers. */
368 //drm_intel_bufmgr_gem_enable_reuse(bufmgr);
370 /* set up nouveau bufmgr */
371 igt_assert(nouveau_device_wrap(nouveau_fd, 0, &ndev) == 0);
372 igt_assert(nouveau_client_new(ndev, &nclient) == 0);
374 /* set up an intel batch buffer */
375 devid = intel_get_drm_devid(intel_fd);
376 intel_batch = intel_batchbuffer_alloc(bufmgr, devid);
379 #define xtest(name) \
383 xtest(i915_nv_sharing);
384 xtest(nv_i915_sharing);
385 xtest(nv_write_i915_cpu_mmap_read);
386 xtest(nv_write_i915_gtt_mmap_read);
387 xtest(i915_import_cpu_mmap);
388 xtest(i915_import_gtt_mmap);
389 xtest(i915_import_pread_pwrite);
390 xtest(i915_blt_fill_nv_read);
393 intel_batchbuffer_free(intel_batch);
395 nouveau_device_del(&ndev);
396 drm_intel_bufmgr_destroy(bufmgr);