2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Jeff McGee <jeff.mcgee@intel.com>
41 #include "intel_bufmgr.h"
42 #include "intel_batchbuffer.h"
43 #include "intel_chipset.h"
44 #include "igt_debugfs.h"
45 #include "ioctl_wrappers.h"
49 static const char sysfs_base_path[] = "/sys/class/drm/card%d/gt_%s_freq_mhz";
60 static int origfreqs[NUMFREQ];
67 { "cur", "r", NULL }, { "min", "rb+", NULL }, { "max", "rb+", NULL }, { "RP0", "r", NULL }, { "RP1", "r", NULL }, { "RPn", "r", NULL }, { NULL, NULL, NULL }
70 static int readval(FILE *filp)
76 scanned = fscanf(filp, "%d", &val);
77 igt_assert(scanned == 1);
82 static void read_freqs(int *freqs)
86 for (i = 0; i < NUMFREQ; i++)
87 freqs[i] = readval(stuff[i].filp);
90 static int do_writeval(FILE *filp, int val, int lerrno)
96 ret = fprintf(filp, "%d", val);
99 /* Expecting specific error */
100 igt_assert(ret == EOF && errno == lerrno);
101 igt_assert(readval(filp) == orig);
103 /* Expecting no error */
104 igt_assert(ret != EOF);
105 igt_assert(readval(filp) == val);
110 #define writeval(filp, val) do_writeval(filp, val, 0)
111 #define writeval_inval(filp, val) do_writeval(filp, val, EINVAL)
113 static void checkit(const int *freqs)
115 igt_assert_cmpint(freqs[MIN], <=, freqs[MAX]);
116 igt_assert_cmpint(freqs[CUR], <=, freqs[MAX]);
117 igt_assert_cmpint(freqs[MIN], <=, freqs[CUR]);
118 igt_assert_cmpint(freqs[RPn], <=, freqs[MIN]);
119 igt_assert_cmpint(freqs[MAX], <=, freqs[RP0]);
120 igt_assert_cmpint(freqs[RP1], <=, freqs[RP0]);
121 igt_assert_cmpint(freqs[RPn], <=, freqs[RP1]);
122 igt_assert(freqs[RP0] != 0);
123 igt_assert(freqs[RP1] != 0);
126 static void matchit(const int *freqs1, const int *freqs2)
128 igt_assert_cmpint(freqs1[CUR], ==, freqs2[CUR]);
129 igt_assert_cmpint(freqs1[MIN], ==, freqs2[MIN]);
130 igt_assert_cmpint(freqs1[MAX], ==, freqs2[MAX]);
131 igt_assert_cmpint(freqs1[RP0], ==, freqs2[RP0]);
132 igt_assert_cmpint(freqs1[RP1], ==, freqs2[RP1]);
133 igt_assert_cmpint(freqs1[RPn], ==, freqs2[RPn]);
136 static void dump(const int *freqs)
140 igt_debug("gt freq (MHz):");
141 for (i = 0; i < NUMFREQ; i++)
142 igt_debug(" %s=%d", stuff[i].name, freqs[i]);
152 static struct load_helper {
155 drm_intel_bufmgr *bufmgr;
156 struct intel_batchbuffer *batch;
157 drm_intel_bo *target_buffer;
160 struct igt_helper_process igt_proc;
161 drm_intel_bo *src, *dst;
164 static void load_helper_signal_handler(int sig)
167 lh.load = lh.load == LOW ? HIGH : LOW;
172 static void emit_store_dword_imm(uint32_t val)
175 struct intel_batchbuffer *batch = lh.batch;
177 cmd = MI_STORE_DWORD_IMM;
179 cmd |= MI_MEM_VIRTUAL;
181 if (intel_gen(lh.devid) >= 8) {
184 OUT_RELOC(lh.target_buffer, I915_GEM_DOMAIN_INSTRUCTION,
185 I915_GEM_DOMAIN_INSTRUCTION, 0);
192 OUT_BATCH(0); /* reserved */
193 OUT_RELOC(lh.target_buffer, I915_GEM_DOMAIN_INSTRUCTION,
194 I915_GEM_DOMAIN_INSTRUCTION, 0);
200 #define LOAD_HELPER_PAUSE_USEC 500
201 #define LOAD_HELPER_BO_SIZE (16*1024*1024)
202 static void load_helper_set_load(enum load load)
204 igt_assert(lh.igt_proc.running);
210 kill(lh.igt_proc.pid, SIGUSR2);
213 static void load_helper_run(enum load load)
216 * FIXME fork helpers won't get cleaned up when started from within a
217 * subtest, so handle the case where it sticks around a bit too long.
219 if (lh.igt_proc.running) {
220 load_helper_set_load(load);
226 igt_fork_helper(&lh.igt_proc) {
229 signal(SIGUSR1, load_helper_signal_handler);
230 signal(SIGUSR2, load_helper_signal_handler);
234 intel_copy_bo(lh.batch, lh.dst, lh.dst,
235 LOAD_HELPER_BO_SIZE);
237 emit_store_dword_imm(val);
238 intel_batchbuffer_flush_on_ring(lh.batch, 0);
241 /* Lower the load by pausing after every submitted
244 usleep(LOAD_HELPER_PAUSE_USEC);
247 /* Map buffer to stall for write completion */
248 drm_intel_bo_map(lh.target_buffer, 0);
249 drm_intel_bo_unmap(lh.target_buffer);
251 igt_debug("load helper sent %u dword writes\n", val);
255 static void load_helper_stop(void)
257 kill(lh.igt_proc.pid, SIGUSR1);
258 igt_wait_helper(&lh.igt_proc);
261 static void load_helper_init(void)
263 lh.devid = intel_get_drm_devid(drm_fd);
264 lh.has_ppgtt = gem_uses_aliasing_ppgtt(drm_fd);
266 /* MI_STORE_DATA can only use GTT address on gen4+/g33 and needs
267 * snoopable mem on pre-gen6. Hence load-helper only works on gen6+, but
268 * that's also all we care about for the rps testcase*/
269 igt_assert(intel_gen(lh.devid) >= 6);
270 lh.bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
271 igt_assert(lh.bufmgr);
273 drm_intel_bufmgr_gem_enable_reuse(lh.bufmgr);
275 lh.batch = intel_batchbuffer_alloc(lh.bufmgr, lh.devid);
276 igt_assert(lh.batch);
278 lh.target_buffer = drm_intel_bo_alloc(lh.bufmgr, "target bo",
280 igt_assert(lh.target_buffer);
282 lh.dst = drm_intel_bo_alloc(lh.bufmgr, "dst bo",
283 LOAD_HELPER_BO_SIZE, 4096);
285 lh.src = drm_intel_bo_alloc(lh.bufmgr, "src bo",
286 LOAD_HELPER_BO_SIZE, 4096);
290 static void load_helper_deinit(void)
292 if (lh.igt_proc.running)
295 if (lh.target_buffer)
296 drm_intel_bo_unreference(lh.target_buffer);
299 intel_batchbuffer_free(lh.batch);
302 drm_intel_bufmgr_destroy(lh.bufmgr);
305 static void stop_rings(void)
308 static const char data[] = "0xf";
310 fd = igt_debugfs_open("i915_ring_stop", O_WRONLY);
313 igt_debug("injecting ring stop\n");
314 igt_assert(write(fd, data, sizeof(data)) == sizeof(data));
319 static bool rings_stopped(void)
322 static char buf[128];
323 unsigned long long val;
325 fd = igt_debugfs_open("i915_ring_stop", O_RDONLY);
328 igt_assert(read(fd, buf, sizeof(buf)) > 0);
331 sscanf(buf, "%llx", &val);
336 static void min_max_config(void (*check)(void))
338 int fmid = (origfreqs[RPn] + origfreqs[RP0]) / 2;
340 /* hw (and so kernel) currently rounds to 50 MHz ... */
341 fmid = fmid / 50 * 50;
343 igt_debug("\nCheck original min and max...\n");
346 igt_debug("\nSet min=RPn and max=RP0...\n");
347 writeval(stuff[MIN].filp, origfreqs[RPn]);
348 writeval(stuff[MAX].filp, origfreqs[RP0]);
351 igt_debug("\nIncrease min to midpoint...\n");
352 writeval(stuff[MIN].filp, fmid);
355 igt_debug("\nIncrease min to RP0...\n");
356 writeval(stuff[MIN].filp, origfreqs[RP0]);
359 igt_debug("\nIncrease min above RP0 (invalid)...\n");
360 writeval_inval(stuff[MIN].filp, origfreqs[RP0] + 1000);
363 igt_debug("\nDecrease max to RPn (invalid)...\n");
364 writeval_inval(stuff[MAX].filp, origfreqs[RPn]);
367 igt_debug("\nDecrease min to midpoint...\n");
368 writeval(stuff[MIN].filp, fmid);
371 igt_debug("\nDecrease min to RPn...\n");
372 writeval(stuff[MIN].filp, origfreqs[RPn]);
375 igt_debug("\nDecrease min below RPn (invalid)...\n");
376 writeval_inval(stuff[MIN].filp, 0);
379 igt_debug("\nDecrease max to midpoint...\n");
380 writeval(stuff[MAX].filp, fmid);
383 igt_debug("\nDecrease max to RPn...\n");
384 writeval(stuff[MAX].filp, origfreqs[RPn]);
387 igt_debug("\nDecrease max below RPn (invalid)...\n");
388 writeval_inval(stuff[MAX].filp, 0);
391 igt_debug("\nIncrease min to RP0 (invalid)...\n");
392 writeval_inval(stuff[MIN].filp, origfreqs[RP0]);
395 igt_debug("\nIncrease max to midpoint...\n");
396 writeval(stuff[MAX].filp, fmid);
399 igt_debug("\nIncrease max to RP0...\n");
400 writeval(stuff[MAX].filp, origfreqs[RP0]);
403 igt_debug("\nIncrease max above RP0 (invalid)...\n");
404 writeval_inval(stuff[MAX].filp, origfreqs[RP0] + 1000);
407 writeval(stuff[MIN].filp, origfreqs[MIN]);
408 writeval(stuff[MAX].filp, origfreqs[MAX]);
411 static void basic_check(void)
420 #define IDLE_WAIT_TIMESTEP_MSEC 100
421 #define IDLE_WAIT_TIMEOUT_MSEC 10000
422 static void idle_check(void)
427 /* Monitor frequencies until cur settles down to min, which should
428 * happen within the allotted time */
433 if (freqs[CUR] == freqs[MIN])
435 usleep(1000 * IDLE_WAIT_TIMESTEP_MSEC);
436 wait += IDLE_WAIT_TIMESTEP_MSEC;
437 } while (wait < IDLE_WAIT_TIMEOUT_MSEC);
439 igt_assert_cmpint(freqs[CUR], ==, freqs[MIN]);
440 igt_debug("Required %d msec to reach cur=min\n", wait);
443 #define LOADED_WAIT_TIMESTEP_MSEC 100
444 #define LOADED_WAIT_TIMEOUT_MSEC 3000
445 static void loaded_check(void)
450 /* Monitor frequencies until cur increases to max, which should
451 * happen within the allotted time */
456 if (freqs[CUR] == freqs[MAX])
458 usleep(1000 * LOADED_WAIT_TIMESTEP_MSEC);
459 wait += LOADED_WAIT_TIMESTEP_MSEC;
460 } while (wait < LOADED_WAIT_TIMEOUT_MSEC);
462 igt_assert_cmpint(freqs[CUR], ==, freqs[MAX]);
463 igt_debug("Required %d msec to reach cur=max\n", wait);
466 #define STABILIZE_WAIT_TIMESTEP_MSEC 100
467 #define STABILIZE_WAIT_TIMEOUT_MSEC 10000
468 static void stabilize_check(int *freqs)
475 usleep(1000 * STABILIZE_WAIT_TIMESTEP_MSEC);
476 wait += STABILIZE_WAIT_TIMESTEP_MSEC;
477 } while (wait < STABILIZE_WAIT_TIMEOUT_MSEC);
479 igt_debug("Waited %d msec to stabilize cur\n", wait);
482 static void reset(void)
484 int pre_freqs[NUMFREQ];
485 int post_freqs[NUMFREQ];
487 igt_debug("Apply low load...\n");
488 load_helper_run(LOW);
489 stabilize_check(pre_freqs);
491 igt_debug("Stop rings...\n");
493 while (rings_stopped())
495 igt_debug("Ring stop cleared\n");
497 igt_debug("Apply high load...\n");
498 load_helper_set_load(HIGH);
501 igt_debug("Apply low load...\n");
502 load_helper_set_load(LOW);
503 stabilize_check(post_freqs);
504 matchit(pre_freqs, post_freqs);
506 igt_debug("Apply high load...\n");
507 load_helper_set_load(HIGH);
510 igt_debug("Removing load...\n");
515 static void pm_rps_exit_handler(int sig)
517 if (origfreqs[MIN] > readval(stuff[MAX].filp)) {
518 writeval(stuff[MAX].filp, origfreqs[MAX]);
519 writeval(stuff[MIN].filp, origfreqs[MIN]);
521 writeval(stuff[MIN].filp, origfreqs[MIN]);
522 writeval(stuff[MAX].filp, origfreqs[MAX]);
525 load_helper_deinit();
531 igt_skip_on_simulation();
534 const int device = drm_get_card();
535 struct junk *junk = stuff;
538 /* Use drm_open_any to verify device existence */
539 drm_fd = drm_open_any();
544 ret = asprintf(&path, sysfs_base_path, device, junk->name);
545 igt_assert(ret != -1);
546 junk->filp = fopen(path, junk->mode);
547 igt_require(junk->filp);
548 setbuf(junk->filp, NULL);
550 val = readval(junk->filp);
551 igt_assert(val >= 0);
553 } while(junk->name != NULL);
555 read_freqs(origfreqs);
557 igt_install_exit_handler(pm_rps_exit_handler);
562 igt_subtest("basic-api")
563 min_max_config(basic_check);
565 igt_subtest("min-max-config-idle")
566 min_max_config(idle_check);
568 igt_subtest("min-max-config-loaded") {
569 load_helper_run(HIGH);
570 min_max_config(loaded_check);