2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Jeff McGee <jeff.mcgee@intel.com>
38 #include "intel_gpu_tools.h"
39 #include "intel_bufmgr.h"
40 #include "intel_batchbuffer.h"
41 #include "igt_debugfs.h"
43 static bool verbose = false;
47 static const char sysfs_base_path[] = "/sys/class/drm/card%d/gt_%s_freq_mhz";
58 static int origfreqs[NUMFREQ];
65 { "cur", "r", NULL }, { "min", "rb+", NULL }, { "max", "rb+", NULL }, { "RP0", "r", NULL }, { "RP1", "r", NULL }, { "RPn", "r", NULL }, { NULL, NULL, NULL }
68 static igt_debugfs_t dfs;
70 static int readval(FILE *filp)
76 scanned = fscanf(filp, "%d", &val);
77 igt_assert(scanned == 1);
82 static void read_freqs(int *freqs)
86 for (i = 0; i < NUMFREQ; i++)
87 freqs[i] = readval(stuff[i].filp);
90 static int do_writeval(FILE *filp, int val, int lerrno)
96 ret = fprintf(filp, "%d", val);
99 /* Expecting specific error */
100 igt_assert(ret == EOF && errno == lerrno);
101 igt_assert(readval(filp) == orig);
103 /* Expecting no error */
104 igt_assert(ret != EOF);
105 igt_assert(readval(filp) == val);
110 #define writeval(filp, val) do_writeval(filp, val, 0)
111 #define writeval_inval(filp, val) do_writeval(filp, val, EINVAL)
113 static void checkit(const int *freqs)
115 igt_assert(freqs[MIN] <= freqs[MAX]);
116 igt_assert(freqs[CUR] <= freqs[MAX]);
117 igt_assert(freqs[MIN] <= freqs[CUR]);
118 igt_assert(freqs[RPn] <= freqs[MIN]);
119 igt_assert(freqs[MAX] <= freqs[RP0]);
120 igt_assert(freqs[RP1] <= freqs[RP0]);
121 igt_assert(freqs[RPn] <= freqs[RP1]);
122 igt_assert(freqs[RP0] != 0);
123 igt_assert(freqs[RP1] != 0);
126 static void matchit(const int *freqs1, const int *freqs2)
128 igt_assert(freqs1[CUR] == freqs2[CUR]);
129 igt_assert(freqs1[MIN] == freqs2[MIN]);
130 igt_assert(freqs1[MAX] == freqs2[MAX]);
131 igt_assert(freqs1[RP0] == freqs2[RP0]);
132 igt_assert(freqs1[RP1] == freqs2[RP1]);
133 igt_assert(freqs1[RPn] == freqs2[RPn]);
136 static void dumpit(const int *freqs)
140 printf("gt freq (MHz):");
141 for (i = 0; i < NUMFREQ; i++)
142 printf(" %s=%d", stuff[i].name, freqs[i]);
146 #define dump(x) if (verbose) dumpit(x)
147 #define log(...) if (verbose) printf(__VA_ARGS__)
154 static struct load_helper {
157 drm_intel_bufmgr *bufmgr;
158 struct intel_batchbuffer *batch;
159 drm_intel_bo *target_buffer;
163 struct igt_helper_process igt_proc;
166 static void load_helper_signal_handler(int sig)
169 lh.load = lh.load == LOW ? HIGH : LOW;
174 static void emit_store_dword_imm(uint32_t val)
177 struct intel_batchbuffer *batch = lh.batch;
179 cmd = MI_STORE_DWORD_IMM;
181 cmd |= MI_MEM_VIRTUAL;
183 if (intel_gen(lh.devid) >= 8) {
186 OUT_RELOC(lh.target_buffer, I915_GEM_DOMAIN_INSTRUCTION,
187 I915_GEM_DOMAIN_INSTRUCTION, 0);
194 OUT_BATCH(0); /* reserved */
195 OUT_RELOC(lh.target_buffer, I915_GEM_DOMAIN_INSTRUCTION,
196 I915_GEM_DOMAIN_INSTRUCTION, 0);
202 #define LOAD_HELPER_PAUSE_USEC 500
203 static void load_helper_run(enum load load)
205 assert(!lh.igt_proc.running);
207 igt_require(lh.ready == true);
211 igt_fork_helper(&lh.igt_proc) {
214 signal(SIGUSR1, load_helper_signal_handler);
215 signal(SIGUSR2, load_helper_signal_handler);
218 emit_store_dword_imm(val);
219 intel_batchbuffer_flush_on_ring(lh.batch, 0);
222 /* Lower the load by pausing after every submitted
225 usleep(LOAD_HELPER_PAUSE_USEC);
228 /* Map buffer to stall for write completion */
229 drm_intel_bo_map(lh.target_buffer, 0);
230 drm_intel_bo_unmap(lh.target_buffer);
232 log("load helper sent %u dword writes\n", val);
236 static void load_helper_set_load(enum load load)
238 assert(lh.igt_proc.running);
244 kill(lh.igt_proc.pid, SIGUSR2);
247 static void load_helper_stop(void)
249 assert(lh.igt_proc.running);
250 kill(lh.igt_proc.pid, SIGUSR1);
251 igt_wait_helper(&lh.igt_proc);
254 /* The load helper resource is used by only some subtests. We attempt to
255 * initialize in igt_fixture but do our igt_require check only if a
256 * subtest attempts to run it */
257 static void load_helper_init(void)
259 lh.devid = intel_get_drm_devid(drm_fd);
260 lh.has_ppgtt = gem_uses_aliasing_ppgtt(drm_fd);
262 /* MI_STORE_DATA can only use GTT address on gen4+/g33 and needs
263 * snoopable mem on pre-gen6. */
264 if (intel_gen(lh.devid) < 6) {
265 log("load helper init failed: pre-gen6 not supported\n");
269 lh.bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
271 log("load helper init failed: buffer manager init\n");
274 drm_intel_bufmgr_gem_enable_reuse(lh.bufmgr);
276 lh.batch = intel_batchbuffer_alloc(lh.bufmgr, lh.devid);
278 log("load helper init failed: batch buffer alloc\n");
282 lh.target_buffer = drm_intel_bo_alloc(lh.bufmgr, "target bo",
284 if (!lh.target_buffer) {
285 log("load helper init failed: target buffer alloc\n");
292 static void load_helper_deinit(void)
294 if (lh.igt_proc.running)
297 if (lh.target_buffer)
298 drm_intel_bo_unreference(lh.target_buffer);
301 intel_batchbuffer_free(lh.batch);
304 drm_intel_bufmgr_destroy(lh.bufmgr);
307 static void stop_rings(void)
310 static const char data[] = "0xf";
312 fd = igt_debugfs_open(&dfs, "i915_ring_stop", O_WRONLY);
315 log("injecting ring stop\n");
316 igt_assert(write(fd, data, sizeof(data)) == sizeof(data));
321 static bool rings_stopped(void)
324 static char buf[128];
325 unsigned long long val;
327 fd = igt_debugfs_open(&dfs, "i915_ring_stop", O_RDONLY);
330 igt_assert(read(fd, buf, sizeof(buf)) > 0);
333 sscanf(buf, "%llx", &val);
338 static void min_max_config(void (*check)(void))
340 int fmid = (origfreqs[RPn] + origfreqs[RP0]) / 2;
342 /* hw (and so kernel) currently rounds to 50 MHz ... */
343 fmid = fmid / 50 * 50;
345 log("\nCheck original min and max...\n");
348 log("\nSet min=RPn and max=RP0...\n");
349 writeval(stuff[MIN].filp, origfreqs[RPn]);
350 writeval(stuff[MAX].filp, origfreqs[RP0]);
353 log("\nIncrease min to midpoint...\n");
354 writeval(stuff[MIN].filp, fmid);
357 log("\nIncrease min to RP0...\n");
358 writeval(stuff[MIN].filp, origfreqs[RP0]);
361 log("\nIncrease min above RP0 (invalid)...\n");
362 writeval_inval(stuff[MIN].filp, origfreqs[RP0] + 1000);
365 log("\nDecrease max to RPn (invalid)...\n");
366 writeval_inval(stuff[MAX].filp, origfreqs[RPn]);
369 log("\nDecrease min to midpoint...\n");
370 writeval(stuff[MIN].filp, fmid);
373 log("\nDecrease min to RPn...\n");
374 writeval(stuff[MIN].filp, origfreqs[RPn]);
377 log("\nDecrease min below RPn (invalid)...\n");
378 writeval_inval(stuff[MIN].filp, 0);
381 log("\nDecrease max to midpoint...\n");
382 writeval(stuff[MAX].filp, fmid);
385 log("\nDecrease max to RPn...\n");
386 writeval(stuff[MAX].filp, origfreqs[RPn]);
389 log("\nDecrease max below RPn (invalid)...\n");
390 writeval_inval(stuff[MAX].filp, 0);
393 log("\nIncrease min to RP0 (invalid)...\n");
394 writeval_inval(stuff[MIN].filp, origfreqs[RP0]);
397 log("\nIncrease max to midpoint...\n");
398 writeval(stuff[MAX].filp, fmid);
401 log("\nIncrease max to RP0...\n");
402 writeval(stuff[MAX].filp, origfreqs[RP0]);
405 log("\nIncrease max above RP0 (invalid)...\n");
406 writeval_inval(stuff[MAX].filp, origfreqs[RP0] + 1000);
409 writeval(stuff[MIN].filp, origfreqs[MIN]);
410 writeval(stuff[MAX].filp, origfreqs[MAX]);
413 static void basic_check(void)
422 #define IDLE_WAIT_TIMESTEP_MSEC 100
423 #define IDLE_WAIT_TIMEOUT_MSEC 3000
424 static void idle_check(void)
429 /* Monitor frequencies until cur settles down to min, which should
430 * happen within the allotted time */
435 if (freqs[CUR] == freqs[MIN])
437 usleep(1000 * IDLE_WAIT_TIMESTEP_MSEC);
438 wait += IDLE_WAIT_TIMESTEP_MSEC;
439 } while (wait < IDLE_WAIT_TIMEOUT_MSEC);
441 igt_assert(freqs[CUR] == freqs[MIN]);
442 log("Required %d msec to reach cur=min\n", wait);
445 #define LOADED_WAIT_TIMESTEP_MSEC 100
446 #define LOADED_WAIT_TIMEOUT_MSEC 3000
447 static void loaded_check(void)
452 /* Monitor frequencies until cur increases to max, which should
453 * happen within the allotted time */
458 if (freqs[CUR] == freqs[MAX])
460 usleep(1000 * LOADED_WAIT_TIMESTEP_MSEC);
461 wait += LOADED_WAIT_TIMESTEP_MSEC;
462 } while (wait < LOADED_WAIT_TIMEOUT_MSEC);
464 igt_assert(freqs[CUR] == freqs[MAX]);
465 log("Required %d msec to reach cur=max\n", wait);
468 #define STABILIZE_WAIT_TIMESTEP_MSEC 100
469 #define STABILIZE_WAIT_TIMEOUT_MSEC 2000
470 static void stabilize_check(int *freqs)
477 usleep(1000 * STABILIZE_WAIT_TIMESTEP_MSEC);
478 wait += STABILIZE_WAIT_TIMESTEP_MSEC;
479 } while (wait < STABILIZE_WAIT_TIMEOUT_MSEC);
481 log("Waited %d msec to stabilize cur\n", wait);
484 static void reset(void)
486 int pre_freqs[NUMFREQ];
487 int post_freqs[NUMFREQ];
489 log("Apply low load...\n");
490 load_helper_run(LOW);
491 stabilize_check(pre_freqs);
493 log("Stop rings...\n");
495 while (rings_stopped())
497 log("Ring stop cleared\n");
499 log("Apply high load...\n");
500 load_helper_set_load(HIGH);
503 log("Apply low load...\n");
504 load_helper_set_load(LOW);
505 stabilize_check(post_freqs);
506 matchit(pre_freqs, post_freqs);
508 log("Apply high load...\n");
509 load_helper_set_load(HIGH);
512 log("Removing load...\n");
517 static void pm_rps_exit_handler(int sig)
519 if (origfreqs[MIN] > readval(stuff[MAX].filp)) {
520 writeval(stuff[MAX].filp, origfreqs[MAX]);
521 writeval(stuff[MIN].filp, origfreqs[MIN]);
523 writeval(stuff[MIN].filp, origfreqs[MIN]);
524 writeval(stuff[MAX].filp, origfreqs[MAX]);
527 load_helper_deinit();
531 static int opt_handler(int opt, int opt_index)
544 /* Mod of igt_subtest_init that adds our extra options */
545 static void subtest_init(int argc, char **argv)
547 struct option long_opts[] = {
548 {"verbose", 0, 0, 'v'}
550 const char *help_str = " -v, --verbose";
553 ret = igt_subtest_init_parse_opts(argc, argv, "v", long_opts,
554 help_str, opt_handler);
557 /* exit with no error for -h/--help */
558 exit(ret == -1 ? 0 : ret);
561 int main(int argc, char **argv)
563 subtest_init(argc, argv);
565 igt_skip_on_simulation();
568 const int device = drm_get_card();
569 struct junk *junk = stuff;
572 /* Use drm_open_any to verify device existence */
573 drm_fd = drm_open_any();
578 ret = asprintf(&path, sysfs_base_path, device, junk->name);
579 igt_assert(ret != -1);
580 junk->filp = fopen(path, junk->mode);
581 igt_require(junk->filp);
582 setbuf(junk->filp, NULL);
584 val = readval(junk->filp);
585 igt_assert(val >= 0);
587 } while(junk->name != NULL);
589 read_freqs(origfreqs);
591 igt_install_exit_handler(pm_rps_exit_handler);
595 igt_debugfs_init(&dfs);
598 igt_subtest("basic-api")
599 min_max_config(basic_check);
601 igt_subtest("min-max-config-idle")
602 min_max_config(idle_check);
604 igt_subtest("min-max-config-loaded") {
605 load_helper_run(HIGH);
606 min_max_config(loaded_check);