2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Jeff McGee <jeff.mcgee@intel.com>
38 #include "intel_gpu_tools.h"
39 #include "intel_bufmgr.h"
40 #include "intel_batchbuffer.h"
41 #include "igt_debugfs.h"
45 static const char sysfs_base_path[] = "/sys/class/drm/card%d/gt_%s_freq_mhz";
56 static int origfreqs[NUMFREQ];
63 { "cur", "r", NULL }, { "min", "rb+", NULL }, { "max", "rb+", NULL }, { "RP0", "r", NULL }, { "RP1", "r", NULL }, { "RPn", "r", NULL }, { NULL, NULL, NULL }
66 static igt_debugfs_t dfs;
68 static int readval(FILE *filp)
74 scanned = fscanf(filp, "%d", &val);
75 igt_assert(scanned == 1);
80 static void read_freqs(int *freqs)
84 for (i = 0; i < NUMFREQ; i++)
85 freqs[i] = readval(stuff[i].filp);
88 static int do_writeval(FILE *filp, int val, int lerrno)
94 ret = fprintf(filp, "%d", val);
97 /* Expecting specific error */
98 igt_assert(ret == EOF && errno == lerrno);
99 igt_assert(readval(filp) == orig);
101 /* Expecting no error */
102 igt_assert(ret != EOF);
103 igt_assert(readval(filp) == val);
108 #define writeval(filp, val) do_writeval(filp, val, 0)
109 #define writeval_inval(filp, val) do_writeval(filp, val, EINVAL)
111 static void checkit(const int *freqs)
113 igt_assert_cmpint(freqs[MIN], <=, freqs[MAX]);
114 igt_assert_cmpint(freqs[CUR], <=, freqs[MAX]);
115 igt_assert_cmpint(freqs[MIN], <=, freqs[CUR]);
116 igt_assert_cmpint(freqs[RPn], <=, freqs[MIN]);
117 igt_assert_cmpint(freqs[MAX], <=, freqs[RP0]);
118 igt_assert_cmpint(freqs[RP1], <=, freqs[RP0]);
119 igt_assert_cmpint(freqs[RPn], <=, freqs[RP1]);
120 igt_assert(freqs[RP0] != 0);
121 igt_assert(freqs[RP1] != 0);
124 static void matchit(const int *freqs1, const int *freqs2)
126 igt_assert_cmpint(freqs1[CUR], ==, freqs2[CUR]);
127 igt_assert_cmpint(freqs1[MIN], ==, freqs2[MIN]);
128 igt_assert_cmpint(freqs1[MAX], ==, freqs2[MAX]);
129 igt_assert_cmpint(freqs1[RP0], ==, freqs2[RP0]);
130 igt_assert_cmpint(freqs1[RP1], ==, freqs2[RP1]);
131 igt_assert_cmpint(freqs1[RPn], ==, freqs2[RPn]);
134 static void dump(const int *freqs)
138 igt_debug("gt freq (MHz):");
139 for (i = 0; i < NUMFREQ; i++)
140 igt_debug(" %s=%d", stuff[i].name, freqs[i]);
150 static struct load_helper {
153 drm_intel_bufmgr *bufmgr;
154 struct intel_batchbuffer *batch;
155 drm_intel_bo *target_buffer;
158 struct igt_helper_process igt_proc;
159 drm_intel_bo *src, *dst;
162 static void load_helper_signal_handler(int sig)
165 lh.load = lh.load == LOW ? HIGH : LOW;
170 static void emit_store_dword_imm(uint32_t val)
173 struct intel_batchbuffer *batch = lh.batch;
175 cmd = MI_STORE_DWORD_IMM;
177 cmd |= MI_MEM_VIRTUAL;
179 if (intel_gen(lh.devid) >= 8) {
182 OUT_RELOC(lh.target_buffer, I915_GEM_DOMAIN_INSTRUCTION,
183 I915_GEM_DOMAIN_INSTRUCTION, 0);
190 OUT_BATCH(0); /* reserved */
191 OUT_RELOC(lh.target_buffer, I915_GEM_DOMAIN_INSTRUCTION,
192 I915_GEM_DOMAIN_INSTRUCTION, 0);
198 #define LOAD_HELPER_PAUSE_USEC 500
199 #define LOAD_HELPER_BO_SIZE (16*1024*1024)
200 static void load_helper_set_load(enum load load)
202 assert(lh.igt_proc.running);
208 kill(lh.igt_proc.pid, SIGUSR2);
211 static void load_helper_run(enum load load)
214 * FIXME fork helpers won't get cleaned up when started from within a
215 * subtest, so handle the case where it sticks around a bit too long.
217 if (lh.igt_proc.running) {
218 load_helper_set_load(load);
224 igt_fork_helper(&lh.igt_proc) {
227 signal(SIGUSR1, load_helper_signal_handler);
228 signal(SIGUSR2, load_helper_signal_handler);
232 intel_copy_bo(lh.batch, lh.dst, lh.dst,
233 LOAD_HELPER_BO_SIZE);
235 emit_store_dword_imm(val);
236 intel_batchbuffer_flush_on_ring(lh.batch, 0);
239 /* Lower the load by pausing after every submitted
242 usleep(LOAD_HELPER_PAUSE_USEC);
245 /* Map buffer to stall for write completion */
246 drm_intel_bo_map(lh.target_buffer, 0);
247 drm_intel_bo_unmap(lh.target_buffer);
249 igt_debug("load helper sent %u dword writes\n", val);
253 static void load_helper_stop(void)
255 kill(lh.igt_proc.pid, SIGUSR1);
256 igt_wait_helper(&lh.igt_proc);
259 static void load_helper_init(void)
261 lh.devid = intel_get_drm_devid(drm_fd);
262 lh.has_ppgtt = gem_uses_aliasing_ppgtt(drm_fd);
264 /* MI_STORE_DATA can only use GTT address on gen4+/g33 and needs
265 * snoopable mem on pre-gen6. Hence load-helper only works on gen6+, but
266 * that's also all we care about for the rps testcase*/
267 igt_assert(intel_gen(lh.devid) >= 6);
268 lh.bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
269 igt_assert(lh.bufmgr);
271 drm_intel_bufmgr_gem_enable_reuse(lh.bufmgr);
273 lh.batch = intel_batchbuffer_alloc(lh.bufmgr, lh.devid);
274 igt_assert(lh.batch);
276 lh.target_buffer = drm_intel_bo_alloc(lh.bufmgr, "target bo",
278 igt_assert(lh.target_buffer);
280 lh.dst = drm_intel_bo_alloc(lh.bufmgr, "dst bo",
281 LOAD_HELPER_BO_SIZE, 4096);
283 lh.src = drm_intel_bo_alloc(lh.bufmgr, "src bo",
284 LOAD_HELPER_BO_SIZE, 4096);
288 static void load_helper_deinit(void)
290 if (lh.igt_proc.running)
293 if (lh.target_buffer)
294 drm_intel_bo_unreference(lh.target_buffer);
297 intel_batchbuffer_free(lh.batch);
300 drm_intel_bufmgr_destroy(lh.bufmgr);
303 static void stop_rings(void)
306 static const char data[] = "0xf";
308 fd = igt_debugfs_open(&dfs, "i915_ring_stop", O_WRONLY);
311 igt_debug("injecting ring stop\n");
312 igt_assert(write(fd, data, sizeof(data)) == sizeof(data));
317 static bool rings_stopped(void)
320 static char buf[128];
321 unsigned long long val;
323 fd = igt_debugfs_open(&dfs, "i915_ring_stop", O_RDONLY);
326 igt_assert(read(fd, buf, sizeof(buf)) > 0);
329 sscanf(buf, "%llx", &val);
334 static void min_max_config(void (*check)(void))
336 int fmid = (origfreqs[RPn] + origfreqs[RP0]) / 2;
338 /* hw (and so kernel) currently rounds to 50 MHz ... */
339 fmid = fmid / 50 * 50;
341 igt_debug("\nCheck original min and max...\n");
344 igt_debug("\nSet min=RPn and max=RP0...\n");
345 writeval(stuff[MIN].filp, origfreqs[RPn]);
346 writeval(stuff[MAX].filp, origfreqs[RP0]);
349 igt_debug("\nIncrease min to midpoint...\n");
350 writeval(stuff[MIN].filp, fmid);
353 igt_debug("\nIncrease min to RP0...\n");
354 writeval(stuff[MIN].filp, origfreqs[RP0]);
357 igt_debug("\nIncrease min above RP0 (invalid)...\n");
358 writeval_inval(stuff[MIN].filp, origfreqs[RP0] + 1000);
361 igt_debug("\nDecrease max to RPn (invalid)...\n");
362 writeval_inval(stuff[MAX].filp, origfreqs[RPn]);
365 igt_debug("\nDecrease min to midpoint...\n");
366 writeval(stuff[MIN].filp, fmid);
369 igt_debug("\nDecrease min to RPn...\n");
370 writeval(stuff[MIN].filp, origfreqs[RPn]);
373 igt_debug("\nDecrease min below RPn (invalid)...\n");
374 writeval_inval(stuff[MIN].filp, 0);
377 igt_debug("\nDecrease max to midpoint...\n");
378 writeval(stuff[MAX].filp, fmid);
381 igt_debug("\nDecrease max to RPn...\n");
382 writeval(stuff[MAX].filp, origfreqs[RPn]);
385 igt_debug("\nDecrease max below RPn (invalid)...\n");
386 writeval_inval(stuff[MAX].filp, 0);
389 igt_debug("\nIncrease min to RP0 (invalid)...\n");
390 writeval_inval(stuff[MIN].filp, origfreqs[RP0]);
393 igt_debug("\nIncrease max to midpoint...\n");
394 writeval(stuff[MAX].filp, fmid);
397 igt_debug("\nIncrease max to RP0...\n");
398 writeval(stuff[MAX].filp, origfreqs[RP0]);
401 igt_debug("\nIncrease max above RP0 (invalid)...\n");
402 writeval_inval(stuff[MAX].filp, origfreqs[RP0] + 1000);
405 writeval(stuff[MIN].filp, origfreqs[MIN]);
406 writeval(stuff[MAX].filp, origfreqs[MAX]);
409 static void basic_check(void)
418 #define IDLE_WAIT_TIMESTEP_MSEC 100
419 #define IDLE_WAIT_TIMEOUT_MSEC 10000
420 static void idle_check(void)
425 /* Monitor frequencies until cur settles down to min, which should
426 * happen within the allotted time */
431 if (freqs[CUR] == freqs[MIN])
433 usleep(1000 * IDLE_WAIT_TIMESTEP_MSEC);
434 wait += IDLE_WAIT_TIMESTEP_MSEC;
435 } while (wait < IDLE_WAIT_TIMEOUT_MSEC);
437 igt_assert_cmpint(freqs[CUR], ==, freqs[MIN]);
438 igt_debug("Required %d msec to reach cur=min\n", wait);
441 #define LOADED_WAIT_TIMESTEP_MSEC 100
442 #define LOADED_WAIT_TIMEOUT_MSEC 3000
443 static void loaded_check(void)
448 /* Monitor frequencies until cur increases to max, which should
449 * happen within the allotted time */
454 if (freqs[CUR] == freqs[MAX])
456 usleep(1000 * LOADED_WAIT_TIMESTEP_MSEC);
457 wait += LOADED_WAIT_TIMESTEP_MSEC;
458 } while (wait < LOADED_WAIT_TIMEOUT_MSEC);
460 igt_assert_cmpint(freqs[CUR], ==, freqs[MAX]);
461 igt_debug("Required %d msec to reach cur=max\n", wait);
464 #define STABILIZE_WAIT_TIMESTEP_MSEC 100
465 #define STABILIZE_WAIT_TIMEOUT_MSEC 10000
466 static void stabilize_check(int *freqs)
473 usleep(1000 * STABILIZE_WAIT_TIMESTEP_MSEC);
474 wait += STABILIZE_WAIT_TIMESTEP_MSEC;
475 } while (wait < STABILIZE_WAIT_TIMEOUT_MSEC);
477 igt_debug("Waited %d msec to stabilize cur\n", wait);
480 static void reset(void)
482 int pre_freqs[NUMFREQ];
483 int post_freqs[NUMFREQ];
485 igt_debug("Apply low load...\n");
486 load_helper_run(LOW);
487 stabilize_check(pre_freqs);
489 igt_debug("Stop rings...\n");
491 while (rings_stopped())
493 igt_debug("Ring stop cleared\n");
495 igt_debug("Apply high load...\n");
496 load_helper_set_load(HIGH);
499 igt_debug("Apply low load...\n");
500 load_helper_set_load(LOW);
501 stabilize_check(post_freqs);
502 matchit(pre_freqs, post_freqs);
504 igt_debug("Apply high load...\n");
505 load_helper_set_load(HIGH);
508 igt_debug("Removing load...\n");
513 static void pm_rps_exit_handler(int sig)
515 if (origfreqs[MIN] > readval(stuff[MAX].filp)) {
516 writeval(stuff[MAX].filp, origfreqs[MAX]);
517 writeval(stuff[MIN].filp, origfreqs[MIN]);
519 writeval(stuff[MIN].filp, origfreqs[MIN]);
520 writeval(stuff[MAX].filp, origfreqs[MAX]);
523 load_helper_deinit();
529 igt_skip_on_simulation();
532 const int device = drm_get_card();
533 struct junk *junk = stuff;
536 /* Use drm_open_any to verify device existence */
537 drm_fd = drm_open_any();
542 ret = asprintf(&path, sysfs_base_path, device, junk->name);
543 igt_assert(ret != -1);
544 junk->filp = fopen(path, junk->mode);
545 igt_require(junk->filp);
546 setbuf(junk->filp, NULL);
548 val = readval(junk->filp);
549 igt_assert(val >= 0);
551 } while(junk->name != NULL);
553 read_freqs(origfreqs);
555 igt_install_exit_handler(pm_rps_exit_handler);
559 igt_debugfs_init(&dfs);
562 igt_subtest("basic-api")
563 min_max_config(basic_check);
565 igt_subtest("min-max-config-idle")
566 min_max_config(idle_check);
568 igt_subtest("min-max-config-loaded") {
569 load_helper_run(HIGH);
570 min_max_config(loaded_check);