2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Jeff McGee <jeff.mcgee@intel.com>
37 #include "intel_gpu_tools.h"
38 #include "intel_bufmgr.h"
39 #include "intel_batchbuffer.h"
40 #include "igt_debugfs.h"
42 static bool verbose = false;
46 static const char sysfs_base_path[] = "/sys/class/drm/card%d/gt_%s_freq_mhz";
57 static int origfreqs[NUMFREQ];
64 { "cur", "r", NULL }, { "min", "rb+", NULL }, { "max", "rb+", NULL }, { "RP0", "r", NULL }, { "RP1", "r", NULL }, { "RPn", "r", NULL }, { NULL, NULL, NULL }
67 static igt_debugfs_t dfs;
69 static int readval(FILE *filp)
75 scanned = fscanf(filp, "%d", &val);
76 igt_assert(scanned == 1);
81 static void read_freqs(int *freqs)
85 for (i = 0; i < NUMFREQ; i++)
86 freqs[i] = readval(stuff[i].filp);
89 static int do_writeval(FILE *filp, int val, int lerrno)
95 ret = fprintf(filp, "%d", val);
98 /* Expecting specific error */
99 igt_assert(ret == EOF && errno == lerrno);
100 igt_assert(readval(filp) == orig);
102 /* Expecting no error */
103 igt_assert(ret != EOF);
104 igt_assert(readval(filp) == val);
109 #define writeval(filp, val) do_writeval(filp, val, 0)
110 #define writeval_inval(filp, val) do_writeval(filp, val, EINVAL)
112 static void setfreq(int val)
114 if (val > readval(stuff[MAX].filp)) {
115 writeval(stuff[MAX].filp, val);
116 writeval(stuff[MIN].filp, val);
118 writeval(stuff[MIN].filp, val);
119 writeval(stuff[MAX].filp, val);
123 static void checkit(const int *freqs)
125 igt_assert(freqs[MIN] <= freqs[MAX]);
126 igt_assert(freqs[CUR] <= freqs[MAX]);
127 igt_assert(freqs[MIN] <= freqs[CUR]);
128 igt_assert(freqs[RPn] <= freqs[MIN]);
129 igt_assert(freqs[MAX] <= freqs[RP0]);
130 igt_assert(freqs[RP1] <= freqs[RP0]);
131 igt_assert(freqs[RPn] <= freqs[RP1]);
132 igt_assert(freqs[RP0] != 0);
133 igt_assert(freqs[RP1] != 0);
136 static void matchit(const int *freqs1, const int *freqs2)
138 igt_assert(freqs1[CUR] == freqs2[CUR]);
139 igt_assert(freqs1[MIN] == freqs2[MIN]);
140 igt_assert(freqs1[MAX] == freqs2[MAX]);
141 igt_assert(freqs1[RP0] == freqs2[RP0]);
142 igt_assert(freqs1[RP1] == freqs2[RP1]);
143 igt_assert(freqs1[RPn] == freqs2[RPn]);
146 static void dumpit(const int *freqs)
150 printf("gt freq (MHz):");
151 for (i = 0; i < NUMFREQ; i++)
152 printf(" %s=%d", stuff[i].name, freqs[i]);
156 #define dump(x) if (verbose) dumpit(x)
157 #define log(...) if (verbose) printf(__VA_ARGS__)
164 static struct load_helper {
167 drm_intel_bufmgr *bufmgr;
168 struct intel_batchbuffer *batch;
169 drm_intel_bo *target_buffer;
173 struct igt_helper_process igt_proc;
176 static void load_helper_signal_handler(int sig)
179 lh.load = lh.load == LOW ? HIGH : LOW;
184 static void emit_store_dword_imm(uint32_t val)
187 struct intel_batchbuffer *batch = lh.batch;
189 cmd = MI_STORE_DWORD_IMM;
191 cmd |= MI_MEM_VIRTUAL;
193 if (intel_gen(lh.devid) >= 8) {
196 OUT_RELOC(lh.target_buffer, I915_GEM_DOMAIN_INSTRUCTION,
197 I915_GEM_DOMAIN_INSTRUCTION, 0);
204 OUT_BATCH(0); /* reserved */
205 OUT_RELOC(lh.target_buffer, I915_GEM_DOMAIN_INSTRUCTION,
206 I915_GEM_DOMAIN_INSTRUCTION, 0);
212 #define LOAD_HELPER_PAUSE_USEC 500
213 static void load_helper_run(enum load load)
215 assert(!lh.igt_proc.running);
217 igt_require(lh.ready == true);
221 igt_fork_helper(&lh.igt_proc) {
224 signal(SIGUSR1, load_helper_signal_handler);
225 signal(SIGUSR2, load_helper_signal_handler);
228 emit_store_dword_imm(val);
229 intel_batchbuffer_flush_on_ring(lh.batch, 0);
232 /* Lower the load by pausing after every submitted
235 usleep(LOAD_HELPER_PAUSE_USEC);
238 /* Map buffer to stall for write completion */
239 drm_intel_bo_map(lh.target_buffer, 0);
240 drm_intel_bo_unmap(lh.target_buffer);
242 log("load helper sent %u dword writes\n", val);
246 static void load_helper_set_load(enum load load)
248 assert(lh.igt_proc.running);
254 kill(lh.igt_proc.pid, SIGUSR2);
257 static void load_helper_stop(void)
259 assert(lh.igt_proc.running);
260 kill(lh.igt_proc.pid, SIGUSR1);
261 igt_wait_helper(&lh.igt_proc);
264 /* The load helper resource is used by only some subtests. We attempt to
265 * initialize in igt_fixture but do our igt_require check only if a
266 * subtest attempts to run it */
267 static void load_helper_init(void)
269 lh.devid = intel_get_drm_devid(drm_fd);
270 lh.has_ppgtt = gem_uses_aliasing_ppgtt(drm_fd);
272 /* MI_STORE_DATA can only use GTT address on gen4+/g33 and needs
273 * snoopable mem on pre-gen6. */
274 if (intel_gen(lh.devid) < 6) {
275 log("load helper init failed: pre-gen6 not supported\n");
279 lh.bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
281 log("load helper init failed: buffer manager init\n");
284 drm_intel_bufmgr_gem_enable_reuse(lh.bufmgr);
286 lh.batch = intel_batchbuffer_alloc(lh.bufmgr, lh.devid);
288 log("load helper init failed: batch buffer alloc\n");
292 lh.target_buffer = drm_intel_bo_alloc(lh.bufmgr, "target bo",
294 if (!lh.target_buffer) {
295 log("load helper init failed: target buffer alloc\n");
302 static void load_helper_deinit(void)
304 if (lh.igt_proc.running)
307 if (lh.target_buffer)
308 drm_intel_bo_unreference(lh.target_buffer);
311 intel_batchbuffer_free(lh.batch);
314 drm_intel_bufmgr_destroy(lh.bufmgr);
317 static void stop_rings(void)
320 static const char data[] = "0xf";
322 fd = igt_debugfs_open(&dfs, "i915_ring_stop", O_WRONLY);
325 log("injecting ring stop\n");
326 igt_assert(write(fd, data, sizeof(data)) == sizeof(data));
331 static bool rings_stopped(void)
334 static char buf[128];
335 unsigned long long val;
337 fd = igt_debugfs_open(&dfs, "i915_ring_stop", O_RDONLY);
340 igt_assert(read(fd, buf, sizeof(buf)) > 0);
343 sscanf(buf, "%llx", &val);
348 static void min_max_config(void (*check)(void))
350 int fmid = (origfreqs[RPn] + origfreqs[RP0]) / 2;
352 log("\nCheck original min and max...\n");
355 log("\nSet min=RPn and max=RP0...\n");
356 writeval(stuff[MIN].filp, origfreqs[RPn]);
357 writeval(stuff[MAX].filp, origfreqs[RP0]);
360 log("\nIncrease min to midpoint...\n");
361 writeval(stuff[MIN].filp, fmid);
364 log("\nIncrease min to RP0...\n");
365 writeval(stuff[MIN].filp, origfreqs[RP0]);
368 log("\nIncrease min above RP0 (invalid)...\n");
369 writeval_inval(stuff[MIN].filp, origfreqs[RP0] + 1000);
372 log("\nDecrease max to RPn (invalid)...\n");
373 writeval_inval(stuff[MAX].filp, origfreqs[RPn]);
376 log("\nDecrease min to midpoint...\n");
377 writeval(stuff[MIN].filp, fmid);
380 log("\nDecrease min to RPn...\n");
381 writeval(stuff[MIN].filp, origfreqs[RPn]);
384 log("\nDecrease min below RPn (invalid)...\n");
385 writeval_inval(stuff[MIN].filp, 0);
388 log("\nDecrease max to midpoint...\n");
389 writeval(stuff[MAX].filp, fmid);
392 log("\nDecrease max to RPn...\n");
393 writeval(stuff[MAX].filp, origfreqs[RPn]);
396 log("\nDecrease max below RPn (invalid)...\n");
397 writeval_inval(stuff[MAX].filp, 0);
400 log("\nIncrease min to RP0 (invalid)...\n");
401 writeval_inval(stuff[MIN].filp, origfreqs[RP0]);
404 log("\nIncrease max to midpoint...\n");
405 writeval(stuff[MAX].filp, fmid);
408 log("\nIncrease max to RP0...\n");
409 writeval(stuff[MAX].filp, origfreqs[RP0]);
412 log("\nIncrease max above RP0 (invalid)...\n");
413 writeval_inval(stuff[MAX].filp, origfreqs[RP0] + 1000);
416 writeval(stuff[MIN].filp, origfreqs[MIN]);
417 writeval(stuff[MAX].filp, origfreqs[MAX]);
420 static void basic_check(void)
429 #define IDLE_WAIT_TIMESTEP_MSEC 100
430 #define IDLE_WAIT_TIMEOUT_MSEC 3000
431 static void idle_check(void)
436 /* Monitor frequencies until cur settles down to min, which should
437 * happen within the allotted time */
442 if (freqs[CUR] == freqs[MIN])
444 usleep(1000 * IDLE_WAIT_TIMESTEP_MSEC);
445 wait += IDLE_WAIT_TIMESTEP_MSEC;
446 } while (wait < IDLE_WAIT_TIMEOUT_MSEC);
448 igt_assert(freqs[CUR] == freqs[MIN]);
449 log("Required %d msec to reach cur=min\n", wait);
452 #define LOADED_WAIT_TIMESTEP_MSEC 100
453 #define LOADED_WAIT_TIMEOUT_MSEC 3000
454 static void loaded_check(void)
459 /* Monitor frequencies until cur increases to max, which should
460 * happen within the allotted time */
465 if (freqs[CUR] == freqs[MAX])
467 usleep(1000 * LOADED_WAIT_TIMESTEP_MSEC);
468 wait += LOADED_WAIT_TIMESTEP_MSEC;
469 } while (wait < LOADED_WAIT_TIMEOUT_MSEC);
471 igt_assert(freqs[CUR] == freqs[MAX]);
472 log("Required %d msec to reach cur=max\n", wait);
475 #define STABILIZE_WAIT_TIMESTEP_MSEC 100
476 #define STABILIZE_WAIT_TIMEOUT_MSEC 2000
477 static void stabilize_check(int *freqs)
484 usleep(1000 * STABILIZE_WAIT_TIMESTEP_MSEC);
485 wait += STABILIZE_WAIT_TIMESTEP_MSEC;
486 } while (wait < STABILIZE_WAIT_TIMEOUT_MSEC);
488 log("Waited %d msec to stabilize cur\n", wait);
491 static void reset(void)
493 int pre_freqs[NUMFREQ];
494 int post_freqs[NUMFREQ];
496 log("Apply low load...\n");
497 load_helper_run(LOW);
498 stabilize_check(pre_freqs);
500 log("Stop rings...\n");
502 while (rings_stopped())
504 log("Ring stop cleared\n");
506 log("Apply high load...\n");
507 load_helper_set_load(HIGH);
510 log("Apply low load...\n");
511 load_helper_set_load(LOW);
512 stabilize_check(post_freqs);
513 matchit(pre_freqs, post_freqs);
515 log("Apply high load...\n");
516 load_helper_set_load(HIGH);
519 log("Removing load...\n");
524 static void pm_rps_exit_handler(int sig)
526 if (origfreqs[MIN] > readval(stuff[MAX].filp)) {
527 writeval(stuff[MAX].filp, origfreqs[MAX]);
528 writeval(stuff[MIN].filp, origfreqs[MIN]);
530 writeval(stuff[MIN].filp, origfreqs[MIN]);
531 writeval(stuff[MAX].filp, origfreqs[MAX]);
534 load_helper_deinit();
538 static int opt_handler(int opt, int opt_index)
551 /* Mod of igt_subtest_init that adds our extra options */
552 static void subtest_init(int argc, char **argv)
554 struct option long_opts[] = {
555 {"verbose", 0, 0, 'v'}
557 const char *help_str = " -v, --verbose";
560 ret = igt_subtest_init_parse_opts(argc, argv, "v", long_opts,
561 help_str, opt_handler);
564 /* exit with no error for -h/--help */
565 exit(ret == -1 ? 0 : ret);
568 int main(int argc, char **argv)
570 subtest_init(argc, argv);
572 igt_skip_on_simulation();
575 const int device = drm_get_card();
576 struct junk *junk = stuff;
579 /* Use drm_open_any to verify device existence */
580 drm_fd = drm_open_any();
585 ret = asprintf(&path, sysfs_base_path, device, junk->name);
586 igt_assert(ret != -1);
587 junk->filp = fopen(path, junk->mode);
588 igt_require(junk->filp);
589 setbuf(junk->filp, NULL);
591 val = readval(junk->filp);
592 igt_assert(val >= 0);
594 } while(junk->name != NULL);
596 read_freqs(origfreqs);
598 igt_install_exit_handler(pm_rps_exit_handler);
602 igt_debugfs_init(&dfs);
605 igt_subtest("basic-api")
606 min_max_config(basic_check);
608 igt_subtest("min-max-config-idle")
609 min_max_config(idle_check);
611 igt_subtest("min-max-config-loaded") {
612 load_helper_run(HIGH);
613 min_max_config(loaded_check);