2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Jeff McGee <jeff.mcgee@intel.com>
40 #include "intel_bufmgr.h"
41 #include "intel_batchbuffer.h"
42 #include "intel_chipset.h"
43 #include "igt_debugfs.h"
44 #include "ioctl_wrappers.h"
48 static const char sysfs_base_path[] = "/sys/class/drm/card%d/gt_%s_freq_mhz";
59 static int origfreqs[NUMFREQ];
66 { "cur", "r", NULL }, { "min", "rb+", NULL }, { "max", "rb+", NULL }, { "RP0", "r", NULL }, { "RP1", "r", NULL }, { "RPn", "r", NULL }, { NULL, NULL, NULL }
69 static int readval(FILE *filp)
75 scanned = fscanf(filp, "%d", &val);
76 igt_assert(scanned == 1);
81 static void read_freqs(int *freqs)
85 for (i = 0; i < NUMFREQ; i++)
86 freqs[i] = readval(stuff[i].filp);
89 static int do_writeval(FILE *filp, int val, int lerrno)
95 ret = fprintf(filp, "%d", val);
98 /* Expecting specific error */
99 igt_assert(ret == EOF && errno == lerrno);
100 igt_assert(readval(filp) == orig);
102 /* Expecting no error */
103 igt_assert(ret != EOF);
104 igt_assert(readval(filp) == val);
109 #define writeval(filp, val) do_writeval(filp, val, 0)
110 #define writeval_inval(filp, val) do_writeval(filp, val, EINVAL)
112 static void checkit(const int *freqs)
114 igt_assert_cmpint(freqs[MIN], <=, freqs[MAX]);
115 igt_assert_cmpint(freqs[CUR], <=, freqs[MAX]);
116 igt_assert_cmpint(freqs[MIN], <=, freqs[CUR]);
117 igt_assert_cmpint(freqs[RPn], <=, freqs[MIN]);
118 igt_assert_cmpint(freqs[MAX], <=, freqs[RP0]);
119 igt_assert_cmpint(freqs[RP1], <=, freqs[RP0]);
120 igt_assert_cmpint(freqs[RPn], <=, freqs[RP1]);
121 igt_assert(freqs[RP0] != 0);
122 igt_assert(freqs[RP1] != 0);
125 static void matchit(const int *freqs1, const int *freqs2)
127 igt_assert_cmpint(freqs1[CUR], ==, freqs2[CUR]);
128 igt_assert_cmpint(freqs1[MIN], ==, freqs2[MIN]);
129 igt_assert_cmpint(freqs1[MAX], ==, freqs2[MAX]);
130 igt_assert_cmpint(freqs1[RP0], ==, freqs2[RP0]);
131 igt_assert_cmpint(freqs1[RP1], ==, freqs2[RP1]);
132 igt_assert_cmpint(freqs1[RPn], ==, freqs2[RPn]);
135 static void dump(const int *freqs)
139 igt_debug("gt freq (MHz):");
140 for (i = 0; i < NUMFREQ; i++)
141 igt_debug(" %s=%d", stuff[i].name, freqs[i]);
151 static struct load_helper {
154 drm_intel_bufmgr *bufmgr;
155 struct intel_batchbuffer *batch;
156 drm_intel_bo *target_buffer;
159 struct igt_helper_process igt_proc;
160 drm_intel_bo *src, *dst;
163 static void load_helper_signal_handler(int sig)
166 lh.load = lh.load == LOW ? HIGH : LOW;
171 static void emit_store_dword_imm(uint32_t val)
174 struct intel_batchbuffer *batch = lh.batch;
176 cmd = MI_STORE_DWORD_IMM;
178 cmd |= MI_MEM_VIRTUAL;
180 if (intel_gen(lh.devid) >= 8) {
183 OUT_RELOC(lh.target_buffer, I915_GEM_DOMAIN_INSTRUCTION,
184 I915_GEM_DOMAIN_INSTRUCTION, 0);
191 OUT_BATCH(0); /* reserved */
192 OUT_RELOC(lh.target_buffer, I915_GEM_DOMAIN_INSTRUCTION,
193 I915_GEM_DOMAIN_INSTRUCTION, 0);
199 #define LOAD_HELPER_PAUSE_USEC 500
200 #define LOAD_HELPER_BO_SIZE (16*1024*1024)
201 static void load_helper_set_load(enum load load)
203 igt_assert(lh.igt_proc.running);
209 kill(lh.igt_proc.pid, SIGUSR2);
212 static void load_helper_run(enum load load)
215 * FIXME fork helpers won't get cleaned up when started from within a
216 * subtest, so handle the case where it sticks around a bit too long.
218 if (lh.igt_proc.running) {
219 load_helper_set_load(load);
225 igt_fork_helper(&lh.igt_proc) {
228 signal(SIGUSR1, load_helper_signal_handler);
229 signal(SIGUSR2, load_helper_signal_handler);
233 intel_copy_bo(lh.batch, lh.dst, lh.src,
234 LOAD_HELPER_BO_SIZE);
236 emit_store_dword_imm(val);
237 intel_batchbuffer_flush_on_ring(lh.batch, 0);
240 /* Lower the load by pausing after every submitted
243 usleep(LOAD_HELPER_PAUSE_USEC);
246 /* Map buffer to stall for write completion */
247 drm_intel_bo_map(lh.target_buffer, 0);
248 drm_intel_bo_unmap(lh.target_buffer);
250 igt_debug("load helper sent %u dword writes\n", val);
254 static void load_helper_stop(void)
256 kill(lh.igt_proc.pid, SIGUSR1);
257 igt_wait_helper(&lh.igt_proc);
260 static void load_helper_init(void)
262 lh.devid = intel_get_drm_devid(drm_fd);
263 lh.has_ppgtt = gem_uses_aliasing_ppgtt(drm_fd);
265 /* MI_STORE_DATA can only use GTT address on gen4+/g33 and needs
266 * snoopable mem on pre-gen6. Hence load-helper only works on gen6+, but
267 * that's also all we care about for the rps testcase*/
268 igt_assert(intel_gen(lh.devid) >= 6);
269 lh.bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
270 igt_assert(lh.bufmgr);
272 drm_intel_bufmgr_gem_enable_reuse(lh.bufmgr);
274 lh.batch = intel_batchbuffer_alloc(lh.bufmgr, lh.devid);
275 igt_assert(lh.batch);
277 lh.target_buffer = drm_intel_bo_alloc(lh.bufmgr, "target bo",
279 igt_assert(lh.target_buffer);
281 lh.dst = drm_intel_bo_alloc(lh.bufmgr, "dst bo",
282 LOAD_HELPER_BO_SIZE, 4096);
284 lh.src = drm_intel_bo_alloc(lh.bufmgr, "src bo",
285 LOAD_HELPER_BO_SIZE, 4096);
289 static void load_helper_deinit(void)
291 if (lh.igt_proc.running)
294 if (lh.target_buffer)
295 drm_intel_bo_unreference(lh.target_buffer);
297 drm_intel_bo_unreference(lh.src);
299 drm_intel_bo_unreference(lh.dst);
302 intel_batchbuffer_free(lh.batch);
305 drm_intel_bufmgr_destroy(lh.bufmgr);
308 static void min_max_config(void (*check)(void))
310 int fmid = (origfreqs[RPn] + origfreqs[RP0]) / 2;
312 /* hw (and so kernel) currently rounds to 50 MHz ... */
313 fmid = fmid / 50 * 50;
315 igt_debug("\nCheck original min and max...\n");
318 igt_debug("\nSet min=RPn and max=RP0...\n");
319 writeval(stuff[MIN].filp, origfreqs[RPn]);
320 writeval(stuff[MAX].filp, origfreqs[RP0]);
323 igt_debug("\nIncrease min to midpoint...\n");
324 writeval(stuff[MIN].filp, fmid);
327 igt_debug("\nIncrease min to RP0...\n");
328 writeval(stuff[MIN].filp, origfreqs[RP0]);
331 igt_debug("\nIncrease min above RP0 (invalid)...\n");
332 writeval_inval(stuff[MIN].filp, origfreqs[RP0] + 1000);
335 igt_debug("\nDecrease max to RPn (invalid)...\n");
336 writeval_inval(stuff[MAX].filp, origfreqs[RPn]);
339 igt_debug("\nDecrease min to midpoint...\n");
340 writeval(stuff[MIN].filp, fmid);
343 igt_debug("\nDecrease min to RPn...\n");
344 writeval(stuff[MIN].filp, origfreqs[RPn]);
347 igt_debug("\nDecrease min below RPn (invalid)...\n");
348 writeval_inval(stuff[MIN].filp, 0);
351 igt_debug("\nDecrease max to midpoint...\n");
352 writeval(stuff[MAX].filp, fmid);
355 igt_debug("\nDecrease max to RPn...\n");
356 writeval(stuff[MAX].filp, origfreqs[RPn]);
359 igt_debug("\nDecrease max below RPn (invalid)...\n");
360 writeval_inval(stuff[MAX].filp, 0);
363 igt_debug("\nIncrease min to RP0 (invalid)...\n");
364 writeval_inval(stuff[MIN].filp, origfreqs[RP0]);
367 igt_debug("\nIncrease max to midpoint...\n");
368 writeval(stuff[MAX].filp, fmid);
371 igt_debug("\nIncrease max to RP0...\n");
372 writeval(stuff[MAX].filp, origfreqs[RP0]);
375 igt_debug("\nIncrease max above RP0 (invalid)...\n");
376 writeval_inval(stuff[MAX].filp, origfreqs[RP0] + 1000);
379 writeval(stuff[MIN].filp, origfreqs[MIN]);
380 writeval(stuff[MAX].filp, origfreqs[MAX]);
383 static void basic_check(void)
392 #define IDLE_WAIT_TIMESTEP_MSEC 100
393 #define IDLE_WAIT_TIMEOUT_MSEC 10000
394 static void idle_check(void)
399 /* Monitor frequencies until cur settles down to min, which should
400 * happen within the allotted time */
405 if (freqs[CUR] == freqs[MIN])
407 usleep(1000 * IDLE_WAIT_TIMESTEP_MSEC);
408 wait += IDLE_WAIT_TIMESTEP_MSEC;
409 } while (wait < IDLE_WAIT_TIMEOUT_MSEC);
411 igt_assert_cmpint(freqs[CUR], ==, freqs[MIN]);
412 igt_debug("Required %d msec to reach cur=min\n", wait);
415 #define LOADED_WAIT_TIMESTEP_MSEC 100
416 #define LOADED_WAIT_TIMEOUT_MSEC 3000
417 static void loaded_check(void)
422 /* Monitor frequencies until cur increases to max, which should
423 * happen within the allotted time */
428 if (freqs[CUR] == freqs[MAX])
430 usleep(1000 * LOADED_WAIT_TIMESTEP_MSEC);
431 wait += LOADED_WAIT_TIMESTEP_MSEC;
432 } while (wait < LOADED_WAIT_TIMEOUT_MSEC);
434 igt_assert_cmpint(freqs[CUR], ==, freqs[MAX]);
435 igt_debug("Required %d msec to reach cur=max\n", wait);
438 #define STABILIZE_WAIT_TIMESTEP_MSEC 100
439 #define STABILIZE_WAIT_TIMEOUT_MSEC 10000
440 static void stabilize_check(int *freqs)
447 usleep(1000 * STABILIZE_WAIT_TIMESTEP_MSEC);
448 wait += STABILIZE_WAIT_TIMESTEP_MSEC;
449 } while (wait < STABILIZE_WAIT_TIMEOUT_MSEC);
451 igt_debug("Waited %d msec to stabilize cur\n", wait);
454 static void reset(void)
456 int pre_freqs[NUMFREQ];
457 int post_freqs[NUMFREQ];
460 * quiescent_gpu upsets the gpu and makes it get pegged to max somehow.
465 igt_debug("Apply low load...\n");
466 load_helper_run(LOW);
467 stabilize_check(pre_freqs);
469 igt_debug("Stop rings...\n");
470 igt_set_stop_rings(STOP_RING_DEFAULTS);
471 while (igt_get_stop_rings())
473 igt_debug("Ring stop cleared\n");
475 igt_debug("Apply high load...\n");
476 load_helper_set_load(HIGH);
479 igt_debug("Apply low load...\n");
480 load_helper_set_load(LOW);
481 stabilize_check(post_freqs);
482 matchit(pre_freqs, post_freqs);
484 igt_debug("Apply high load...\n");
485 load_helper_set_load(HIGH);
488 igt_debug("Removing load...\n");
493 static void blocking(void)
495 int pre_freqs[NUMFREQ];
496 int post_freqs[NUMFREQ];
498 int fd = drm_open_any();
502 * quiescent_gpu upsets the gpu and makes it get pegged to max somehow.
507 igt_debug("Apply low load...\n");
508 load_helper_run(LOW);
509 stabilize_check(pre_freqs);
514 igt_debug("Kick gpu hard ...\n");
515 /* This relies on the blocking waits in quiescent_gpu and the kernel
516 * boost logic to ramp the gpu to full load. */
517 gem_quiescent_gpu(fd);
518 gem_quiescent_gpu(fd);
520 igt_debug("Apply low load again...\n");
521 load_helper_run(LOW);
522 stabilize_check(post_freqs);
524 matchit(pre_freqs, post_freqs);
526 igt_debug("Removing load...\n");
530 static void pm_rps_exit_handler(int sig)
532 if (origfreqs[MIN] > readval(stuff[MAX].filp)) {
533 writeval(stuff[MAX].filp, origfreqs[MAX]);
534 writeval(stuff[MIN].filp, origfreqs[MIN]);
536 writeval(stuff[MIN].filp, origfreqs[MIN]);
537 writeval(stuff[MAX].filp, origfreqs[MAX]);
540 load_helper_deinit();
546 igt_skip_on_simulation();
549 const int device = drm_get_card();
550 struct junk *junk = stuff;
553 /* Use drm_open_any to verify device existence */
554 drm_fd = drm_open_any();
559 ret = asprintf(&path, sysfs_base_path, device, junk->name);
560 igt_assert(ret != -1);
561 junk->filp = fopen(path, junk->mode);
562 igt_require(junk->filp);
563 setbuf(junk->filp, NULL);
565 val = readval(junk->filp);
566 igt_assert(val >= 0);
568 } while(junk->name != NULL);
570 read_freqs(origfreqs);
572 igt_install_exit_handler(pm_rps_exit_handler);
577 igt_subtest("basic-api")
578 min_max_config(basic_check);
580 igt_subtest("min-max-config-idle")
581 min_max_config(idle_check);
583 igt_subtest("min-max-config-loaded") {
584 load_helper_run(HIGH);
585 min_max_config(loaded_check);
592 igt_subtest("blocking")