tests/pm_rpm.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Paulo Zanoni <paulo.r.zanoni@intel.com>
  25  *
  26  */
  27
  28 #include <stdio.h>
  29 #include <stdint.h>
  30 #include <stdbool.h>
  31 #include <string.h>
  32
  33 #include <unistd.h>
  34 #include <fcntl.h>
  35 #include <dirent.h>
  36 #include <sys/ioctl.h>
  37 #include <sys/mman.h>
  38 #include <sys/types.h>
  39 #include <sys/stat.h>
  40 #include <linux/i2c.h>
  41 #include <linux/i2c-dev.h>
  42
  43 #include <drm.h>
  44
  45 #include "drmtest.h"
  46 #include "intel_batchbuffer.h"
  47 #include "intel_io.h"
  48 #include "intel_chipset.h"
  49 #include "ioctl_wrappers.h"
  50 #include "igt_aux.h"
  51 #include "igt_kms.h"
  52 #include "igt_debugfs.h"
  53
  54 /* One day, this will be on your libdrm. */
  55 #define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2
  56
  57 #define MSR_PC8_RES     0x630
  58 #define MSR_PC9_RES     0x631
  59 #define MSR_PC10_RES    0x632
  60
  61 #define MAX_CONNECTORS  32
  62 #define MAX_ENCODERS    32
  63 #define MAX_CRTCS       16
  64
  65 #define POWER_DIR "/sys/devices/pci0000:00/0000:00:02.0/power"
  66
  67 enum pc8_status {
  68         PC8_ENABLED,
  69         PC8_DISABLED
  70 };
  71
  72 enum screen_type {
  73         SCREEN_TYPE_LPSP,
  74         SCREEN_TYPE_NON_LPSP,
  75         SCREEN_TYPE_ANY,
  76 };
  77
  78 enum plane_type {
  79         PLANE_OVERLAY,
  80         PLANE_PRIMARY,
  81         PLANE_CURSOR,
  82 };
  83
  84 /* Wait flags */
  85 #define DONT_WAIT       0
  86 #define WAIT_STATUS     1
  87 #define WAIT_PC8_RES    2
  88 #define WAIT_EXTRA      4
  89 #define USE_DPMS        8
  90
  91 int drm_fd, msr_fd, pm_status_fd, pc8_status_fd;
  92 bool has_runtime_pm, has_pc8;
  93 struct mode_set_data ms_data;
  94
  95 /* Stuff used when creating FBs and mode setting. */
  96 struct mode_set_data {
  97         drmModeResPtr res;
  98         drmModeConnectorPtr connectors[MAX_CONNECTORS];
  99         drmModePropertyBlobPtr edids[MAX_CONNECTORS];
 100
 101         uint32_t devid;
 102 };
 103
 104 /* Stuff we query at different times so we can compare. */
 105 struct compare_data {
 106         drmModeResPtr res;
 107         drmModeEncoderPtr encoders[MAX_ENCODERS];
 108         drmModeConnectorPtr connectors[MAX_CONNECTORS];
 109         drmModeCrtcPtr crtcs[MAX_CRTCS];
 110         drmModePropertyBlobPtr edids[MAX_CONNECTORS];
 111 };
 112
 113 struct modeset_params {
 114         uint32_t crtc_id;
 115         uint32_t connector_id;
 116         struct igt_fb fb;
 117         drmModeModeInfoPtr mode;
 118 };
 119
 120 struct modeset_params lpsp_mode_params;
 121 struct modeset_params non_lpsp_mode_params;
 122 struct modeset_params *default_mode_params;
 123
 124 /* If the read fails, then the machine doesn't support PC8+ residencies. */
 125 static bool supports_pc8_plus_residencies(void)
 126 {
 127         int rc;
 128         uint64_t val;
 129
 130         rc = pread(msr_fd, &val, sizeof(uint64_t), MSR_PC8_RES);
 131         if (rc != sizeof(val))
 132                 return false;
 133         rc = pread(msr_fd, &val, sizeof(uint64_t), MSR_PC9_RES);
 134         if (rc != sizeof(val))
 135                 return false;
 136         rc = pread(msr_fd, &val, sizeof(uint64_t), MSR_PC10_RES);
 137         if (rc != sizeof(val))
 138                 return false;
 139
 140         return true;
 141 }
 142
 143 static uint64_t get_residency(uint32_t type)
 144 {
 145         int rc;
 146         uint64_t ret;
 147
 148         rc = pread(msr_fd, &ret, sizeof(uint64_t), type);
 149         igt_assert(rc == sizeof(ret));
 150
 151         return ret;
 152 }
 153
 154 static bool pc8_plus_residency_changed(unsigned int timeout_sec)
 155 {
 156         unsigned int i;
 157         uint64_t res_pc8, res_pc9, res_pc10;
 158         int to_sleep = 100 * 1000;
 159
 160         res_pc8 = get_residency(MSR_PC8_RES);
 161         res_pc9 = get_residency(MSR_PC9_RES);
 162         res_pc10 = get_residency(MSR_PC10_RES);
 163
 164         for (i = 0; i < timeout_sec * 1000 * 1000; i += to_sleep) {
 165                 if (res_pc8 != get_residency(MSR_PC8_RES) ||
 166                     res_pc9 != get_residency(MSR_PC9_RES) ||
 167                     res_pc10 != get_residency(MSR_PC10_RES)) {
 168                         return true;
 169                 }
 170                 usleep(to_sleep);
 171         }
 172
 173         return false;
 174 }
 175
 176 static enum pc8_status get_pc8_status(void)
 177 {
 178         ssize_t n_read;
 179         char buf[150]; /* The whole file has less than 100 chars. */
 180
 181         lseek(pc8_status_fd, 0, SEEK_SET);
 182         n_read = read(pc8_status_fd, buf, ARRAY_SIZE(buf));
 183         igt_assert(n_read >= 0);
 184         buf[n_read] = '\0';
 185
 186         if (strstr(buf, "\nEnabled: yes\n"))
 187                 return PC8_ENABLED;
 188         else
 189                 return PC8_DISABLED;
 190 }
 191
 192 static bool wait_for_pc8_status(enum pc8_status status)
 193 {
 194         int i;
 195         int hundred_ms = 100 * 1000, ten_s = 10 * 1000 * 1000;
 196
 197         for (i = 0; i < ten_s; i += hundred_ms) {
 198                 if (get_pc8_status() == status)
 199                         return true;
 200
 201                 usleep(hundred_ms);
 202         }
 203
 204         return false;
 205 }
 206
 207 static bool wait_for_suspended(void)
 208 {
 209         if (has_pc8 && !has_runtime_pm)
 210                 return wait_for_pc8_status(PC8_ENABLED);
 211         else
 212                 return igt_wait_for_pm_status(IGT_RUNTIME_PM_STATUS_SUSPENDED);
 213 }
 214
 215 static bool wait_for_active(void)
 216 {
 217         if (has_pc8 && !has_runtime_pm)
 218                 return wait_for_pc8_status(PC8_DISABLED);
 219         else
 220                 return igt_wait_for_pm_status(IGT_RUNTIME_PM_STATUS_ACTIVE);
 221 }
 222
 223 static void disable_all_screens_dpms(struct mode_set_data *data)
 224 {
 225         int i;
 226
 227         for (i = 0; i < data->res->count_connectors; i++) {
 228                 drmModeConnectorPtr c = data->connectors[i];
 229
 230                 kmstest_set_connector_dpms(drm_fd, c, DRM_MODE_DPMS_OFF);
 231         }
 232 }
 233
 234 static void disable_all_screens(struct mode_set_data *data)
 235 {
 236         kmstest_unset_all_crtcs(drm_fd, data->res);
 237 }
 238
 239 #define disable_all_screens_and_wait(data) do { \
 240         disable_all_screens(data); \
 241         igt_assert(wait_for_suspended()); \
 242 } while (0)
 243
 244 static void disable_or_dpms_all_screens(struct mode_set_data *data, bool dpms)
 245 {
 246         if (dpms)
 247                 disable_all_screens_dpms(&ms_data);
 248         else
 249                 disable_all_screens(&ms_data);
 250 }
 251
 252 #define disable_or_dpms_all_screens_and_wait(data, dpms) do { \
 253         disable_or_dpms_all_screens((data), (dpms)); \
 254         igt_assert(wait_for_suspended()); \
 255 } while (0)
 256
 257 static bool init_modeset_params_for_type(struct mode_set_data *data,
 258                                          struct modeset_params *params,
 259                                          enum screen_type type)
 260 {
 261         int i;
 262         uint32_t connector_id = 0;
 263         drmModeModeInfoPtr mode = NULL;
 264         cairo_t *cr;
 265
 266         for (i = 0; i < data->res->count_connectors; i++) {
 267                 drmModeConnectorPtr c = data->connectors[i];
 268
 269                 if (type == SCREEN_TYPE_LPSP &&
 270                     c->connector_type != DRM_MODE_CONNECTOR_eDP)
 271                         continue;
 272
 273                 if (type == SCREEN_TYPE_NON_LPSP &&
 274                     c->connector_type == DRM_MODE_CONNECTOR_eDP)
 275                         continue;
 276
 277                 if (c->connection == DRM_MODE_CONNECTED && c->count_modes) {
 278                         connector_id = c->connector_id;
 279                         mode = &c->modes[0];
 280                         break;
 281                 }
 282         }
 283
 284         if (!connector_id)
 285                 return false;
 286
 287         igt_create_fb(drm_fd, mode->hdisplay, mode->vdisplay,
 288                       DRM_FORMAT_XRGB8888, false, &params->fb);
 289         cr = igt_get_cairo_ctx(drm_fd, &params->fb);
 290         igt_paint_test_pattern(cr, mode->hdisplay, mode->vdisplay);
 291         cairo_destroy(cr);
 292
 293         params->crtc_id = data->res->crtcs[0];
 294         params->connector_id = connector_id;
 295         params->mode = mode;
 296
 297         return true;
 298 }
 299
 300 static void init_modeset_cached_params(struct mode_set_data *data)
 301 {
 302         bool lpsp, non_lpsp;
 303
 304         lpsp = init_modeset_params_for_type(data, &lpsp_mode_params,
 305                                             SCREEN_TYPE_LPSP);
 306         non_lpsp = init_modeset_params_for_type(data, &non_lpsp_mode_params,
 307                                                 SCREEN_TYPE_NON_LPSP);
 308
 309         if (lpsp)
 310                 default_mode_params = &lpsp_mode_params;
 311         else if (non_lpsp)
 312                 default_mode_params = &non_lpsp_mode_params;
 313         else
 314                 default_mode_params = NULL;
 315 }
 316
 317 static bool set_mode_for_params(struct modeset_params *params)
 318 {
 319         int rc;
 320
 321         rc = drmModeSetCrtc(drm_fd, params->crtc_id, params->fb.fb_id, 0, 0,
 322                             &params->connector_id, 1, params->mode);
 323         return (rc == 0);
 324 }
 325
 326 #define set_mode_for_params_and_wait(params) do { \
 327         igt_assert(set_mode_for_params(params)); \
 328         igt_assert(wait_for_active()); \
 329 } while (0)
 330
 331 static bool enable_one_screen_with_type(struct mode_set_data *data,
 332                                         enum screen_type type)
 333 {
 334         struct modeset_params *params = NULL;
 335
 336         switch (type) {
 337         case SCREEN_TYPE_ANY:
 338                 params = default_mode_params;
 339                 break;
 340         case SCREEN_TYPE_LPSP:
 341                 params = &lpsp_mode_params;
 342                 break;
 343         case SCREEN_TYPE_NON_LPSP:
 344                 params = &non_lpsp_mode_params;
 345                 break;
 346         default:
 347                 igt_assert(0);
 348         }
 349
 350         if (!params)
 351                 return false;
 352
 353         return set_mode_for_params(params);
 354 }
 355
 356 static void enable_one_screen(struct mode_set_data *data)
 357 {
 358         /* SKIP if there are no connected screens. */
 359         igt_require(enable_one_screen_with_type(data, SCREEN_TYPE_ANY));
 360 }
 361
 362 #define enable_one_screen_and_wait(data) do { \
 363         enable_one_screen(data); \
 364         igt_assert(wait_for_active()); \
 365 } while (0)
 366
 367 static drmModePropertyBlobPtr get_connector_edid(drmModeConnectorPtr connector,
 368                                                  int index)
 369 {
 370         bool found;
 371         uint64_t prop_value;
 372         drmModePropertyPtr prop;
 373         drmModePropertyBlobPtr blob = NULL;
 374
 375         found = kmstest_get_property(drm_fd, connector->connector_id,
 376                                      DRM_MODE_OBJECT_CONNECTOR, "EDID",
 377                                      NULL, &prop_value, &prop);
 378
 379         if (found) {
 380                 igt_assert(prop->flags & DRM_MODE_PROP_BLOB);
 381                 igt_assert(prop->count_blobs == 0);
 382
 383                 blob = drmModeGetPropertyBlob(drm_fd, prop_value);
 384
 385                 drmModeFreeProperty(prop);
 386         }
 387
 388         return blob;
 389 }
 390
 391 static void init_mode_set_data(struct mode_set_data *data)
 392 {
 393         int i;
 394
 395         data->res = drmModeGetResources(drm_fd);
 396         igt_assert(data->res);
 397         igt_assert(data->res->count_connectors <= MAX_CONNECTORS);
 398
 399         for (i = 0; i < data->res->count_connectors; i++) {
 400                 data->connectors[i] = drmModeGetConnector(drm_fd,
 401                                                 data->res->connectors[i]);
 402                 data->edids[i] = get_connector_edid(data->connectors[i], i);
 403         }
 404
 405         data->devid = intel_get_drm_devid(drm_fd);
 406
 407         igt_set_vt_graphics_mode();
 408
 409         init_modeset_cached_params(&ms_data);
 410 }
 411
 412 static void fini_mode_set_data(struct mode_set_data *data)
 413 {
 414         int i;
 415
 416         for (i = 0; i < data->res->count_connectors; i++) {
 417                 drmModeFreeConnector(data->connectors[i]);
 418                 drmModeFreePropertyBlob(data->edids[i]);
 419         }
 420         drmModeFreeResources(data->res);
 421 }
 422
 423 static void get_drm_info(struct compare_data *data)
 424 {
 425         int i;
 426
 427         data->res = drmModeGetResources(drm_fd);
 428         igt_assert(data->res);
 429
 430         igt_assert(data->res->count_connectors <= MAX_CONNECTORS);
 431         igt_assert(data->res->count_encoders <= MAX_ENCODERS);
 432         igt_assert(data->res->count_crtcs <= MAX_CRTCS);
 433
 434         for (i = 0; i < data->res->count_connectors; i++) {
 435                 data->connectors[i] = drmModeGetConnector(drm_fd,
 436                                                 data->res->connectors[i]);
 437                 data->edids[i] = get_connector_edid(data->connectors[i], i);
 438         }
 439         for (i = 0; i < data->res->count_encoders; i++)
 440                 data->encoders[i] = drmModeGetEncoder(drm_fd,
 441                                                 data->res->encoders[i]);
 442         for (i = 0; i < data->res->count_crtcs; i++)
 443                 data->crtcs[i] = drmModeGetCrtc(drm_fd, data->res->crtcs[i]);
 444 }
 445
 446 static void free_drm_info(struct compare_data *data)
 447 {
 448         int i;
 449
 450         for (i = 0; i < data->res->count_connectors; i++) {
 451                 drmModeFreeConnector(data->connectors[i]);
 452                 drmModeFreePropertyBlob(data->edids[i]);
 453         }
 454         for (i = 0; i < data->res->count_encoders; i++)
 455                 drmModeFreeEncoder(data->encoders[i]);
 456         for (i = 0; i < data->res->count_crtcs; i++)
 457                 drmModeFreeCrtc(data->crtcs[i]);
 458
 459         drmModeFreeResources(data->res);
 460 }
 461
 462 #define COMPARE(d1, d2, data) igt_assert(d1->data == d2->data)
 463 #define COMPARE_ARRAY(d1, d2, size, data) do { \
 464         for (i = 0; i < size; i++) \
 465                 igt_assert(d1->data[i] == d2->data[i]); \
 466 } while (0)
 467
 468 static void assert_drm_resources_equal(struct compare_data *d1,
 469                                        struct compare_data *d2)
 470 {
 471         COMPARE(d1, d2, res->count_connectors);
 472         COMPARE(d1, d2, res->count_encoders);
 473         COMPARE(d1, d2, res->count_crtcs);
 474         COMPARE(d1, d2, res->min_width);
 475         COMPARE(d1, d2, res->max_width);
 476         COMPARE(d1, d2, res->min_height);
 477         COMPARE(d1, d2, res->max_height);
 478 }
 479
 480 static void assert_modes_equal(drmModeModeInfoPtr m1, drmModeModeInfoPtr m2)
 481 {
 482         COMPARE(m1, m2, clock);
 483         COMPARE(m1, m2, hdisplay);
 484         COMPARE(m1, m2, hsync_start);
 485         COMPARE(m1, m2, hsync_end);
 486         COMPARE(m1, m2, htotal);
 487         COMPARE(m1, m2, hskew);
 488         COMPARE(m1, m2, vdisplay);
 489         COMPARE(m1, m2, vsync_start);
 490         COMPARE(m1, m2, vsync_end);
 491         COMPARE(m1, m2, vtotal);
 492         COMPARE(m1, m2, vscan);
 493         COMPARE(m1, m2, vrefresh);
 494         COMPARE(m1, m2, flags);
 495         COMPARE(m1, m2, type);
 496         igt_assert(strcmp(m1->name, m2->name) == 0);
 497 }
 498
 499 static void assert_drm_connectors_equal(drmModeConnectorPtr c1,
 500                                         drmModeConnectorPtr c2)
 501 {
 502         int i;
 503
 504         COMPARE(c1, c2, connector_id);
 505         COMPARE(c1, c2, connector_type);
 506         COMPARE(c1, c2, connector_type_id);
 507         COMPARE(c1, c2, mmWidth);
 508         COMPARE(c1, c2, mmHeight);
 509         COMPARE(c1, c2, count_modes);
 510         COMPARE(c1, c2, count_props);
 511         COMPARE(c1, c2, count_encoders);
 512         COMPARE_ARRAY(c1, c2, c1->count_props, props);
 513         COMPARE_ARRAY(c1, c2, c1->count_encoders, encoders);
 514
 515         for (i = 0; i < c1->count_modes; i++)
 516                 assert_modes_equal(&c1->modes[0], &c2->modes[0]);
 517 }
 518
 519 static void assert_drm_encoders_equal(drmModeEncoderPtr e1,
 520                                       drmModeEncoderPtr e2)
 521 {
 522         COMPARE(e1, e2, encoder_id);
 523         COMPARE(e1, e2, encoder_type);
 524         COMPARE(e1, e2, possible_crtcs);
 525         COMPARE(e1, e2, possible_clones);
 526 }
 527
 528 static void assert_drm_crtcs_equal(drmModeCrtcPtr c1, drmModeCrtcPtr c2)
 529 {
 530         COMPARE(c1, c2, crtc_id);
 531 }
 532
 533 static void assert_drm_edids_equal(drmModePropertyBlobPtr e1,
 534                                    drmModePropertyBlobPtr e2)
 535 {
 536         if (!e1 && !e2)
 537                 return;
 538         igt_assert(e1 && e2);
 539
 540         COMPARE(e1, e2, id);
 541         COMPARE(e1, e2, length);
 542
 543         igt_assert(memcmp(e1->data, e2->data, e1->length) == 0);
 544 }
 545
 546 static void assert_drm_infos_equal(struct compare_data *d1,
 547                                    struct compare_data *d2)
 548 {
 549         int i;
 550
 551         assert_drm_resources_equal(d1, d2);
 552
 553         for (i = 0; i < d1->res->count_connectors; i++) {
 554                 assert_drm_connectors_equal(d1->connectors[i],
 555                                             d2->connectors[i]);
 556                 assert_drm_edids_equal(d1->edids[i], d2->edids[i]);
 557         }
 558
 559         for (i = 0; i < d1->res->count_encoders; i++)
 560                 assert_drm_encoders_equal(d1->encoders[i], d2->encoders[i]);
 561
 562         for (i = 0; i < d1->res->count_crtcs; i++)
 563                 assert_drm_crtcs_equal(d1->crtcs[i], d2->crtcs[i]);
 564 }
 565
 566 /* We could check the checksum too, but just the header is probably enough. */
 567 static bool edid_is_valid(const unsigned char *edid)
 568 {
 569         char edid_header[] = {
 570                 0x0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x0,
 571         };
 572
 573         return (memcmp(edid, edid_header, sizeof(edid_header)) == 0);
 574 }
 575
 576 static int count_drm_valid_edids(struct mode_set_data *data)
 577 {
 578         int i, ret = 0;
 579
 580         for (i = 0; i < data->res->count_connectors; i++)
 581                 if (data->edids[i] && edid_is_valid(data->edids[i]->data))
 582                         ret++;
 583         return ret;
 584 }
 585
 586 static bool i2c_edid_is_valid(int fd)
 587 {
 588         int rc;
 589         unsigned char edid[128] = {};
 590         struct i2c_msg msgs[] = {
 591                 { /* Start at 0. */
 592                         .addr = 0x50,
 593                         .flags = 0,
 594                         .len = 1,
 595                         .buf = edid,
 596                 }, { /* Now read the EDID. */
 597                         .addr = 0x50,
 598                         .flags = I2C_M_RD,
 599                         .len = 128,
 600                         .buf = edid,
 601                 }
 602         };
 603         struct i2c_rdwr_ioctl_data msgset = {
 604                 .msgs = msgs,
 605                 .nmsgs = 2,
 606         };
 607
 608         rc = ioctl(fd, I2C_RDWR, &msgset);
 609         return (rc >= 0) ? edid_is_valid(edid) : false;
 610 }
 611
 612 static int count_i2c_valid_edids(void)
 613 {
 614         int fd, ret = 0;
 615         DIR *dir;
 616
 617         struct dirent *dirent;
 618         char full_name[32];
 619
 620         dir = opendir("/dev/");
 621         igt_assert(dir);
 622
 623         while ((dirent = readdir(dir))) {
 624                 if (strncmp(dirent->d_name, "i2c-", 4) == 0) {
 625                         snprintf(full_name, 32, "/dev/%s", dirent->d_name);
 626                         fd = open(full_name, O_RDWR);
 627                         igt_assert(fd != -1);
 628                         if (i2c_edid_is_valid(fd))
 629                                 ret++;
 630                         close(fd);
 631                 }
 632         }
 633
 634         closedir(dir);
 635
 636         return ret;
 637 }
 638
 639 static void test_i2c(struct mode_set_data *data)
 640 {
 641         int i2c_edids = count_i2c_valid_edids();
 642         int drm_edids = count_drm_valid_edids(data);
 643
 644         igt_assert_cmpint(i2c_edids, ==, drm_edids);
 645 }
 646
 647 static void setup_pc8(void)
 648 {
 649         has_pc8 = false;
 650
 651         /* Only Haswell supports the PC8 feature. */
 652         if (!IS_HASWELL(ms_data.devid) && !IS_BROADWELL(ms_data.devid))
 653                 return;
 654
 655         /* Make sure our Kernel supports MSR and the module is loaded. */
 656         igt_assert(system("modprobe -q msr > /dev/null 2>&1") != -1);
 657
 658         msr_fd = open("/dev/cpu/0/msr", O_RDONLY);
 659         igt_assert_f(msr_fd >= 0,
 660                      "Can't open /dev/cpu/0/msr.\n");
 661
 662         /* Non-ULT machines don't support PC8+. */
 663         if (!supports_pc8_plus_residencies())
 664                 return;
 665
 666         pc8_status_fd = open("/sys/kernel/debug/dri/0/i915_pc8_status",
 667                              O_RDONLY);
 668         igt_assert_f(pc8_status_fd >= 0,
 669                      "Can't open /sys/kernel/debug/dri/0/i915_pc8_status");
 670
 671         has_pc8 = true;
 672 }
 673
 674 /* If we want to actually reach PC8+ states, we need to properly configure all
 675  * the devices on the system to allow this. This function will try to setup the
 676  * things we know we need, but won't scream in case anything fails: we don't
 677  * know which devices are present on your machine, so we can't really expect
 678  * anything, just try to help with the more common problems. */
 679 static void setup_non_graphics_runtime_pm(void)
 680 {
 681         int fd, i;
 682         char *file_name;
 683
 684         /* Disk runtime PM policies. */
 685         file_name = malloc(PATH_MAX);
 686         for (i = 0; ; i++) {
 687
 688                 snprintf(file_name, PATH_MAX,
 689                          "/sys/class/scsi_host/host%d/link_power_management_policy",
 690                          i);
 691
 692                 fd = open(file_name, O_WRONLY);
 693                 if (fd < 0)
 694                         break;
 695
 696                 write(fd, "min_power\n", 10);
 697                 close(fd);
 698         }
 699         free(file_name);
 700
 701         /* Audio runtime PM policies. */
 702         fd = open("/sys/module/snd_hda_intel/parameters/power_save", O_WRONLY);
 703         if (fd >= 0) {
 704                 write(fd, "1\n", 2);
 705                 close(fd);
 706         }
 707         fd = open("/sys/bus/pci/devices/0000:00:03.0/power/control", O_WRONLY);
 708         if (fd >= 0) {
 709                 write(fd, "auto\n", 5);
 710                 close(fd);
 711         }
 712 }
 713
 714 static void setup_environment(void)
 715 {
 716         drm_fd = drm_open_any();
 717         igt_assert(drm_fd >= 0);
 718
 719         igt_require_f(drmSetMaster(drm_fd) == 0, "Can't become DRM master, "
 720                       "please check if no other DRM client is running.\n");
 721
 722         init_mode_set_data(&ms_data);
 723
 724         setup_non_graphics_runtime_pm();
 725
 726         has_runtime_pm = igt_setup_runtime_pm();
 727         setup_pc8();
 728
 729         igt_info("Runtime PM support: %d\n", has_runtime_pm);
 730         igt_info("PC8 residency support: %d\n", has_pc8);
 731
 732         igt_require(has_runtime_pm);
 733
 734 }
 735
 736 static void teardown_environment(void)
 737 {
 738         fini_mode_set_data(&ms_data);
 739         drmClose(drm_fd);
 740         close(msr_fd);
 741         if (has_pc8)
 742                 close(pc8_status_fd);
 743 }
 744
 745 static void basic_subtest(void)
 746 {
 747         disable_all_screens_and_wait(&ms_data);
 748
 749         enable_one_screen_and_wait(&ms_data);
 750 }
 751
 752 static void pc8_residency_subtest(void)
 753 {
 754         igt_require(has_pc8);
 755
 756         /* Make sure PC8+ residencies move! */
 757         disable_all_screens(&ms_data);
 758         igt_assert_f(pc8_plus_residency_changed(120),
 759                      "Machine is not reaching PC8+ states, please check its "
 760                      "configuration.\n");
 761
 762         /* Make sure PC8+ residencies stop! */
 763         enable_one_screen(&ms_data);
 764         igt_assert_f(!pc8_plus_residency_changed(10),
 765                      "PC8+ residency didn't stop with screen enabled.\n");
 766 }
 767
 768 static void modeset_subtest(enum screen_type type, int rounds, int wait_flags)
 769 {
 770         int i;
 771
 772         if (wait_flags & WAIT_PC8_RES)
 773                 igt_require(has_pc8);
 774
 775         for (i = 0; i < rounds; i++) {
 776                 if (wait_flags & USE_DPMS)
 777                         disable_all_screens_dpms(&ms_data);
 778                 else
 779                         disable_all_screens(&ms_data);
 780
 781                 if (wait_flags & WAIT_STATUS)
 782                         igt_assert(wait_for_suspended());
 783                 if (wait_flags & WAIT_PC8_RES)
 784                         igt_assert(pc8_plus_residency_changed(120));
 785                 if (wait_flags & WAIT_EXTRA)
 786                         sleep(5);
 787
 788                 /* If we skip this line it's because the type of screen we want
 789                  * is not connected. */
 790                 igt_require(enable_one_screen_with_type(&ms_data, type));
 791                 if (wait_flags & WAIT_STATUS)
 792                         igt_assert(wait_for_active());
 793                 if (wait_flags & WAIT_PC8_RES)
 794                         igt_assert(!pc8_plus_residency_changed(5));
 795                 if (wait_flags & WAIT_EXTRA)
 796                         sleep(5);
 797         }
 798 }
 799
 800 /* Test of the DRM resources reported by the IOCTLs are still the same. This
 801  * ensures we still see the monitors with the same eyes. We get the EDIDs and
 802  * compare them, which ensures we use DP AUX or GMBUS depending on what's
 803  * connected. */
 804 static void drm_resources_equal_subtest(void)
 805 {
 806         struct compare_data pre_suspend, during_suspend, post_suspend;
 807
 808         enable_one_screen_and_wait(&ms_data);
 809         get_drm_info(&pre_suspend);
 810         igt_assert(wait_for_active());
 811
 812         disable_all_screens_and_wait(&ms_data);
 813         get_drm_info(&during_suspend);
 814         igt_assert(wait_for_suspended());
 815
 816         enable_one_screen_and_wait(&ms_data);
 817         get_drm_info(&post_suspend);
 818         igt_assert(wait_for_active());
 819
 820         assert_drm_infos_equal(&pre_suspend, &during_suspend);
 821         assert_drm_infos_equal(&pre_suspend, &post_suspend);
 822
 823         free_drm_info(&pre_suspend);
 824         free_drm_info(&during_suspend);
 825         free_drm_info(&post_suspend);
 826 }
 827
 828 static void i2c_subtest_check_environment(void)
 829 {
 830         int i2c_dev_files = 0;
 831         DIR *dev_dir;
 832         struct dirent *dirent;
 833
 834         /* Make sure the /dev/i2c-* files exist. */
 835         igt_assert(system("modprobe -q i2c-dev > /dev/null 2>&1") != -1);
 836
 837         dev_dir = opendir("/dev");
 838         igt_assert(dev_dir);
 839         while ((dirent = readdir(dev_dir))) {
 840                 if (strncmp(dirent->d_name, "i2c-", 4) == 0)
 841                         i2c_dev_files++;
 842         }
 843         closedir(dev_dir);
 844         igt_require(i2c_dev_files);
 845 }
 846
 847 /* Try to use raw I2C, which also needs interrupts. */
 848 static void i2c_subtest(void)
 849 {
 850         i2c_subtest_check_environment();
 851
 852         enable_one_screen_and_wait(&ms_data);
 853
 854         disable_all_screens_and_wait(&ms_data);
 855         test_i2c(&ms_data);
 856         igt_assert(wait_for_suspended());
 857
 858         enable_one_screen(&ms_data);
 859 }
 860
 861 static void read_full_file(const char *name)
 862 {
 863         int rc, fd;
 864         char buf[128];
 865
 866         igt_assert_f(wait_for_suspended(), "File: %s\n", name);
 867
 868         fd = open(name, O_RDONLY);
 869         if (fd < 0)
 870                 return;
 871
 872         do {
 873                 rc = read(fd, buf, ARRAY_SIZE(buf));
 874         } while (rc == ARRAY_SIZE(buf));
 875
 876         rc = close(fd);
 877         igt_assert(rc == 0);
 878
 879         igt_assert_f(wait_for_suspended(), "File: %s\n", name);
 880 }
 881
 882 static void read_files_from_dir(const char *name, int level)
 883 {
 884         DIR *dir;
 885         struct dirent *dirent;
 886         char *full_name;
 887         int rc;
 888
 889         dir = opendir(name);
 890         igt_assert(dir);
 891
 892         full_name = malloc(PATH_MAX);
 893
 894         igt_assert(level < 128);
 895
 896         while ((dirent = readdir(dir))) {
 897                 struct stat stat_buf;
 898
 899                 if (strcmp(dirent->d_name, ".") == 0)
 900                         continue;
 901                 if (strcmp(dirent->d_name, "..") == 0)
 902                         continue;
 903
 904                 snprintf(full_name, PATH_MAX, "%s/%s", name, dirent->d_name);
 905
 906                 rc = lstat(full_name, &stat_buf);
 907                 igt_assert(rc == 0);
 908
 909                 if (S_ISDIR(stat_buf.st_mode))
 910                         read_files_from_dir(full_name, level + 1);
 911
 912                 if (S_ISREG(stat_buf.st_mode))
 913                         read_full_file(full_name);
 914         }
 915
 916         free(full_name);
 917         closedir(dir);
 918 }
 919
 920 /* This test will probably pass, with a small chance of hanging the machine in
 921  * case of bugs. Many of the bugs exercised by this patch just result in dmesg
 922  * errors, so a "pass" here should be confirmed by a check on dmesg. */
 923 static void debugfs_read_subtest(void)
 924 {
 925         const char *path = "/sys/kernel/debug/dri/0";
 926         DIR *dir;
 927
 928         dir = opendir(path);
 929         igt_require_f(dir, "Can't open the debugfs directory\n");
 930         closedir(dir);
 931
 932         disable_all_screens_and_wait(&ms_data);
 933
 934         read_files_from_dir(path, 0);
 935 }
 936
 937 /* Read the comment on debugfs_read_subtest(). */
 938 static void sysfs_read_subtest(void)
 939 {
 940         const char *path = "/sys/devices/pci0000:00/0000:00:02.0";
 941         DIR *dir;
 942
 943         dir = opendir(path);
 944         igt_require_f(dir, "Can't open the sysfs directory\n");
 945         closedir(dir);
 946
 947         disable_all_screens_and_wait(&ms_data);
 948
 949         read_files_from_dir(path, 0);
 950 }
 951
 952 /* Make sure we don't suspend when we have the i915_forcewake_user file open. */
 953 static void debugfs_forcewake_user_subtest(void)
 954 {
 955         int fd, rc;
 956
 957         igt_require(intel_gen(ms_data.devid) >= 6);
 958
 959         disable_all_screens_and_wait(&ms_data);
 960
 961         fd = igt_open_forcewake_handle();
 962         igt_require(fd >= 0);
 963
 964         if (has_runtime_pm) {
 965                 igt_assert(wait_for_active());
 966                 sleep(10);
 967                 igt_assert(wait_for_active());
 968         } else {
 969                 igt_assert(wait_for_suspended());
 970         }
 971
 972         rc = close(fd);
 973         igt_assert(rc == 0);
 974
 975         igt_assert(wait_for_suspended());
 976 }
 977
 978 static void gem_mmap_subtest(bool gtt_mmap)
 979 {
 980         int i;
 981         uint32_t handle;
 982         int buf_size = 8192;
 983         uint8_t *gem_buf;
 984
 985         /* Create, map and set data while the device is active. */
 986         enable_one_screen_and_wait(&ms_data);
 987
 988         handle = gem_create(drm_fd, buf_size);
 989
 990         if (gtt_mmap)
 991                 gem_buf = gem_mmap__gtt(drm_fd, handle, buf_size,
 992                                         PROT_READ | PROT_WRITE);
 993         else
 994                 gem_buf = gem_mmap__cpu(drm_fd, handle, buf_size, 0);
 995
 996
 997         for (i = 0; i < buf_size; i++)
 998                 gem_buf[i] = i & 0xFF;
 999
1000         for (i = 0; i < buf_size; i++)
1001                 igt_assert(gem_buf[i] == (i & 0xFF));
1002
1003         /* Now suspend, read and modify. */
1004         disable_all_screens_and_wait(&ms_data);
1005
1006         for (i = 0; i < buf_size; i++)
1007                 igt_assert(gem_buf[i] == (i & 0xFF));
1008         igt_assert(wait_for_suspended());
1009
1010         for (i = 0; i < buf_size; i++)
1011                 gem_buf[i] = (~i & 0xFF);
1012         igt_assert(wait_for_suspended());
1013
1014         /* Now resume and see if it's still there. */
1015         enable_one_screen_and_wait(&ms_data);
1016         for (i = 0; i < buf_size; i++)
1017                 igt_assert(gem_buf[i] == (~i & 0xFF));
1018
1019         igt_assert(munmap(gem_buf, buf_size) == 0);
1020
1021         /* Now the opposite: suspend, and try to create the mmap while
1022          * suspended. */
1023         disable_all_screens_and_wait(&ms_data);
1024
1025         if (gtt_mmap)
1026                 gem_buf = gem_mmap__gtt(drm_fd, handle, buf_size,
1027                                         PROT_READ | PROT_WRITE);
1028         else
1029                 gem_buf = gem_mmap__cpu(drm_fd, handle, buf_size, 0);
1030
1031         igt_assert(wait_for_suspended());
1032
1033         for (i = 0; i < buf_size; i++)
1034                 gem_buf[i] = i & 0xFF;
1035
1036         for (i = 0; i < buf_size; i++)
1037                 igt_assert(gem_buf[i] == (i & 0xFF));
1038
1039         igt_assert(wait_for_suspended());
1040
1041         /* Resume and check if it's still there. */
1042         enable_one_screen_and_wait(&ms_data);
1043         for (i = 0; i < buf_size; i++)
1044                 igt_assert(gem_buf[i] == (i & 0xFF));
1045
1046         igt_assert(munmap(gem_buf, buf_size) == 0);
1047         gem_close(drm_fd, handle);
1048 }
1049
1050 static void gem_pread_subtest(void)
1051 {
1052         int i;
1053         uint32_t handle;
1054         int buf_size = 8192;
1055         uint8_t *cpu_buf, *read_buf;
1056
1057         cpu_buf = malloc(buf_size);
1058         read_buf = malloc(buf_size);
1059         igt_assert(cpu_buf);
1060         igt_assert(read_buf);
1061         memset(cpu_buf, 0, buf_size);
1062         memset(read_buf, 0, buf_size);
1063
1064         /* Create and set data while the device is active. */
1065         enable_one_screen_and_wait(&ms_data);
1066
1067         handle = gem_create(drm_fd, buf_size);
1068
1069         for (i = 0; i < buf_size; i++)
1070                 cpu_buf[i] = i & 0xFF;
1071
1072         gem_write(drm_fd, handle, 0, cpu_buf, buf_size);
1073
1074         gem_read(drm_fd, handle, 0, read_buf, buf_size);
1075
1076         for (i = 0; i < buf_size; i++)
1077                 igt_assert(cpu_buf[i] == read_buf[i]);
1078
1079         /* Now suspend, read and modify. */
1080         disable_all_screens_and_wait(&ms_data);
1081
1082         memset(read_buf, 0, buf_size);
1083         gem_read(drm_fd, handle, 0, read_buf, buf_size);
1084
1085         for (i = 0; i < buf_size; i++)
1086                 igt_assert(cpu_buf[i] == read_buf[i]);
1087         igt_assert(wait_for_suspended());
1088
1089         for (i = 0; i < buf_size; i++)
1090                 cpu_buf[i] = (~i & 0xFF);
1091         gem_write(drm_fd, handle, 0, cpu_buf, buf_size);
1092         igt_assert(wait_for_suspended());
1093
1094         /* Now resume and see if it's still there. */
1095         enable_one_screen_and_wait(&ms_data);
1096
1097         memset(read_buf, 0, buf_size);
1098         gem_read(drm_fd, handle, 0, read_buf, buf_size);
1099
1100         for (i = 0; i < buf_size; i++)
1101                 igt_assert(cpu_buf[i] == read_buf[i]);
1102
1103         gem_close(drm_fd, handle);
1104
1105         free(cpu_buf);
1106         free(read_buf);
1107 }
1108
1109 /* Paints a square of color $color, size $width x $height, at position $x x $y
1110  * of $dst_handle, which contains pitch $pitch. */
1111 static void submit_blt_cmd(uint32_t dst_handle, uint16_t x, uint16_t y,
1112                            uint16_t width, uint16_t height, uint32_t pitch,
1113                            uint32_t color, uint32_t *presumed_dst_offset)
1114 {
1115         int i, reloc_pos;
1116         uint32_t batch_handle;
1117         int batch_size = 8 * sizeof(uint32_t);
1118         uint32_t batch_buf[batch_size];
1119         struct drm_i915_gem_execbuffer2 execbuf = {};
1120         struct drm_i915_gem_exec_object2 objs[2] = {{}, {}};
1121         struct drm_i915_gem_relocation_entry relocs[1] = {{}};
1122         struct drm_i915_gem_wait gem_wait;
1123
1124         i = 0;
1125
1126         if (intel_gen(ms_data.devid) >= 8)
1127                 batch_buf[i++] = XY_COLOR_BLT_CMD_NOLEN |
1128                                  XY_COLOR_BLT_WRITE_ALPHA |
1129                                  XY_COLOR_BLT_WRITE_RGB | 0x5;
1130         else
1131                 batch_buf[i++] = XY_COLOR_BLT_CMD_NOLEN |
1132                                  XY_COLOR_BLT_WRITE_ALPHA |
1133                                  XY_COLOR_BLT_WRITE_RGB | 0x4;
1134         batch_buf[i++] = (3 << 24) | (0xF0 << 16) | (pitch);
1135         batch_buf[i++] = (y << 16) | x;
1136         batch_buf[i++] = ((y + height) << 16) | (x + width);
1137         reloc_pos = i;
1138         batch_buf[i++] = *presumed_dst_offset;
1139         if (intel_gen(ms_data.devid) >= 8)
1140                 batch_buf[i++] = 0;
1141         batch_buf[i++] = color;
1142
1143         batch_buf[i++] = MI_BATCH_BUFFER_END;
1144         if (intel_gen(ms_data.devid) < 8)
1145                 batch_buf[i++] = MI_NOOP;
1146
1147         igt_assert(i * sizeof(uint32_t) == batch_size);
1148
1149         batch_handle = gem_create(drm_fd, batch_size);
1150         gem_write(drm_fd, batch_handle, 0, batch_buf, batch_size);
1151
1152         relocs[0].target_handle = dst_handle;
1153         relocs[0].delta = 0;
1154         relocs[0].offset = reloc_pos * sizeof(uint32_t);
1155         relocs[0].presumed_offset = *presumed_dst_offset;
1156         relocs[0].read_domains = 0;
1157         relocs[0].write_domain = I915_GEM_DOMAIN_RENDER;
1158
1159         objs[0].handle = dst_handle;
1160         objs[0].alignment = 64;
1161
1162         objs[1].handle = batch_handle;
1163         objs[1].relocation_count = 1;
1164         objs[1].relocs_ptr = (uintptr_t)relocs;
1165
1166         execbuf.buffers_ptr = (uintptr_t)objs;
1167         execbuf.buffer_count = 2;
1168         execbuf.batch_len = batch_size;
1169         execbuf.flags = I915_EXEC_BLT;
1170         i915_execbuffer2_set_context_id(execbuf, 0);
1171
1172         do_ioctl(drm_fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf);
1173
1174         *presumed_dst_offset = relocs[0].presumed_offset;
1175
1176         gem_wait.flags = 0;
1177         gem_wait.timeout_ns = 10000000000LL; /* 10s */
1178
1179         gem_wait.bo_handle = batch_handle;
1180         do_ioctl(drm_fd, DRM_IOCTL_I915_GEM_WAIT, &gem_wait);
1181
1182         gem_wait.bo_handle = dst_handle;
1183         do_ioctl(drm_fd, DRM_IOCTL_I915_GEM_WAIT, &gem_wait);
1184
1185         gem_close(drm_fd, batch_handle);
1186 }
1187
1188 /* Make sure we can submit a batch buffer and verify its result. */
1189 static void gem_execbuf_subtest(void)
1190 {
1191         int x, y;
1192         uint32_t handle;
1193         int bpp = 4;
1194         int pitch = 128 * bpp;
1195         int dst_size = 128 * 128 * bpp; /* 128x128 square */
1196         uint32_t *cpu_buf;
1197         uint32_t presumed_offset = 0;
1198         int sq_x = 5, sq_y = 10, sq_w = 15, sq_h = 20;
1199         uint32_t color;
1200
1201         /* Create and set data while the device is active. */
1202         enable_one_screen_and_wait(&ms_data);
1203
1204         handle = gem_create(drm_fd, dst_size);
1205
1206         cpu_buf = malloc(dst_size);
1207         igt_assert(cpu_buf);
1208         memset(cpu_buf, 0, dst_size);
1209         gem_write(drm_fd, handle, 0, cpu_buf, dst_size);
1210
1211         /* Now suspend and try it. */
1212         disable_all_screens_and_wait(&ms_data);
1213
1214         color = 0x12345678;
1215         submit_blt_cmd(handle, sq_x, sq_y, sq_w, sq_h, pitch, color,
1216                        &presumed_offset);
1217         igt_assert(wait_for_suspended());
1218
1219         gem_read(drm_fd, handle, 0, cpu_buf, dst_size);
1220         igt_assert(wait_for_suspended());
1221         for (y = 0; y < 128; y++) {
1222                 for (x = 0; x < 128; x++) {
1223                         uint32_t px = cpu_buf[y * 128 + x];
1224
1225                         if (y >= sq_y && y < (sq_y + sq_h) &&
1226                             x >= sq_x && x < (sq_x + sq_w))
1227                                 igt_assert(px == color);
1228                         else
1229                                 igt_assert(px == 0);
1230                 }
1231         }
1232
1233         /* Now resume and check for it again. */
1234         enable_one_screen_and_wait(&ms_data);
1235
1236         memset(cpu_buf, 0, dst_size);
1237         gem_read(drm_fd, handle, 0, cpu_buf, dst_size);
1238         for (y = 0; y < 128; y++) {
1239                 for (x = 0; x < 128; x++) {
1240                         uint32_t px = cpu_buf[y * 128 + x];
1241
1242                         if (y >= sq_y && y < (sq_y + sq_h) &&
1243                             x >= sq_x && x < (sq_x + sq_w))
1244                                 igt_assert(px == color);
1245                         else
1246                                 igt_assert(px == 0);
1247                 }
1248         }
1249
1250         /* Now we'll do the opposite: do the blt while active, then read while
1251          * suspended. We use the same spot, but a different color. As a bonus,
1252          * we're testing the presumed_offset from the previous command. */
1253         color = 0x87654321;
1254         submit_blt_cmd(handle, sq_x, sq_y, sq_w, sq_h, pitch, color,
1255                        &presumed_offset);
1256
1257         disable_all_screens_and_wait(&ms_data);
1258
1259         memset(cpu_buf, 0, dst_size);
1260         gem_read(drm_fd, handle, 0, cpu_buf, dst_size);
1261         for (y = 0; y < 128; y++) {
1262                 for (x = 0; x < 128; x++) {
1263                         uint32_t px = cpu_buf[y * 128 + x];
1264
1265                         if (y >= sq_y && y < (sq_y + sq_h) &&
1266                             x >= sq_x && x < (sq_x + sq_w))
1267                                 igt_assert(px == color);
1268                         else
1269                                 igt_assert(px == 0);
1270                 }
1271         }
1272
1273         gem_close(drm_fd, handle);
1274
1275         free(cpu_buf);
1276 }
1277
1278 /* Assuming execbuf already works, let's see what happens when we force many
1279  * suspend/resume cycles with commands. */
1280 static void gem_execbuf_stress_subtest(int rounds, int wait_flags)
1281 {
1282         int i;
1283         int batch_size = 4 * sizeof(uint32_t);
1284         uint32_t batch_buf[batch_size];
1285         uint32_t handle;
1286         struct drm_i915_gem_execbuffer2 execbuf = {};
1287         struct drm_i915_gem_exec_object2 objs[1] = {{}};
1288
1289         if (wait_flags & WAIT_PC8_RES)
1290                 igt_require(has_pc8);
1291
1292         i = 0;
1293         batch_buf[i++] = MI_NOOP;
1294         batch_buf[i++] = MI_NOOP;
1295         batch_buf[i++] = MI_BATCH_BUFFER_END;
1296         batch_buf[i++] = MI_NOOP;
1297         igt_assert(i * sizeof(uint32_t) == batch_size);
1298
1299         disable_all_screens_and_wait(&ms_data);
1300
1301         handle = gem_create(drm_fd, batch_size);
1302         gem_write(drm_fd, handle, 0, batch_buf, batch_size);
1303
1304         objs[0].handle = handle;
1305
1306         execbuf.buffers_ptr = (uintptr_t)objs;
1307         execbuf.buffer_count = 1;
1308         execbuf.batch_len = batch_size;
1309         execbuf.flags = I915_EXEC_RENDER;
1310         i915_execbuffer2_set_context_id(execbuf, 0);
1311
1312         for (i = 0; i < rounds; i++) {
1313                 do_ioctl(drm_fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf);
1314
1315                 if (wait_flags & WAIT_STATUS)
1316                         igt_assert(wait_for_suspended());
1317                 if (wait_flags & WAIT_PC8_RES)
1318                         igt_assert(pc8_plus_residency_changed(120));
1319                 if (wait_flags & WAIT_EXTRA)
1320                         sleep(5);
1321         }
1322
1323         gem_close(drm_fd, handle);
1324 }
1325
1326 /* When this test was written, it triggered WARNs and DRM_ERRORs on dmesg. */
1327 static void gem_idle_subtest(void)
1328 {
1329         disable_all_screens_and_wait(&ms_data);
1330
1331         sleep(5);
1332
1333         gem_quiescent_gpu(drm_fd);
1334 }
1335
1336 /* This also triggered WARNs on dmesg at some point. */
1337 static void reg_read_ioctl_subtest(void)
1338 {
1339         struct drm_i915_reg_read rr = {
1340                 .offset = 0x2358, /* render ring timestamp */
1341         };
1342
1343         disable_all_screens_and_wait(&ms_data);
1344
1345         do_ioctl(drm_fd, DRM_IOCTL_I915_REG_READ, &rr);
1346
1347         igt_assert(wait_for_suspended());
1348 }
1349
1350 static bool device_in_pci_d3(void)
1351 {
1352         struct pci_device *pci_dev;
1353         int rc;
1354         uint16_t val;
1355
1356         pci_dev = intel_get_pci_device();
1357
1358         rc = pci_device_cfg_read_u16(pci_dev, &val, 0xd4);
1359         igt_assert(rc == 0);
1360
1361         return (val & 0x3) == 0x3;
1362 }
1363
1364 static void pci_d3_state_subtest(void)
1365 {
1366         igt_require(has_runtime_pm);
1367
1368         disable_all_screens_and_wait(&ms_data);
1369
1370         igt_assert(device_in_pci_d3());
1371
1372         enable_one_screen_and_wait(&ms_data);
1373
1374         igt_assert(!device_in_pci_d3());
1375 }
1376
1377 static void stay_subtest(void)
1378 {
1379         disable_all_screens_and_wait(&ms_data);
1380
1381         while (1)
1382                 sleep(600);
1383 }
1384
1385 static void system_suspend_subtest(void)
1386 {
1387         disable_all_screens_and_wait(&ms_data);
1388         igt_system_suspend_autoresume();
1389         igt_assert(wait_for_suspended());
1390 }
1391
1392 /* Enable a screen, activate DPMS, then do a modeset. At some point our driver
1393  * produced WARNs on this case. */
1394 static void dpms_mode_unset_subtest(enum screen_type type)
1395 {
1396         disable_all_screens_and_wait(&ms_data);
1397
1398         igt_require(enable_one_screen_with_type(&ms_data, type));
1399         igt_assert(wait_for_active());
1400
1401         disable_all_screens_dpms(&ms_data);
1402         igt_assert(wait_for_suspended());
1403
1404         disable_all_screens_and_wait(&ms_data);
1405 }
1406
1407 static void fill_igt_fb(struct igt_fb *fb, uint32_t color)
1408 {
1409         int i;
1410         uint32_t *ptr;
1411
1412         ptr = gem_mmap__gtt(drm_fd, fb->gem_handle, fb->size, PROT_WRITE);
1413         for (i = 0; i < fb->size/sizeof(uint32_t); i++)
1414                 ptr[i] = color;
1415         igt_assert(munmap(ptr, fb->size) == 0);
1416 }
1417
1418 /* At some point, this test triggered WARNs in the Kernel. */
1419 static void cursor_subtest(bool dpms)
1420 {
1421         int rc;
1422         struct igt_fb cursor_fb1, cursor_fb2, cursor_fb3;
1423         uint32_t crtc_id;
1424
1425         disable_all_screens_and_wait(&ms_data);
1426
1427         igt_require(default_mode_params);
1428         crtc_id = default_mode_params->crtc_id;
1429
1430         igt_create_fb(drm_fd, 64, 64, DRM_FORMAT_ARGB8888, false, &cursor_fb1);
1431         igt_create_fb(drm_fd, 64, 64, DRM_FORMAT_ARGB8888, false, &cursor_fb2);
1432         igt_create_fb(drm_fd, 64, 64, DRM_FORMAT_ARGB8888, true, &cursor_fb3);
1433
1434         fill_igt_fb(&cursor_fb1, 0xFF00FFFF);
1435         fill_igt_fb(&cursor_fb2, 0xFF00FF00);
1436         fill_igt_fb(&cursor_fb3, 0xFFFF0000);
1437
1438         set_mode_for_params_and_wait(default_mode_params);
1439
1440         rc = drmModeSetCursor(drm_fd, crtc_id, cursor_fb1.gem_handle,
1441                               cursor_fb1.width, cursor_fb1.height);
1442         igt_assert(rc == 0);
1443         rc = drmModeMoveCursor(drm_fd, crtc_id, 0, 0);
1444         igt_assert(rc == 0);
1445         igt_assert(wait_for_active());
1446
1447         disable_or_dpms_all_screens_and_wait(&ms_data, dpms);
1448
1449         /* First, just move the cursor. */
1450         rc = drmModeMoveCursor(drm_fd, crtc_id, 1, 1);
1451         igt_assert(rc == 0);
1452         igt_assert(wait_for_suspended());
1453
1454         /* Then unset it, and set a new one. */
1455         rc = drmModeSetCursor(drm_fd, crtc_id, 0, 0, 0);
1456         igt_assert(rc == 0);
1457         igt_assert(wait_for_suspended());
1458
1459         rc = drmModeSetCursor(drm_fd, crtc_id, cursor_fb2.gem_handle,
1460                               cursor_fb1.width, cursor_fb2.height);
1461         igt_assert(rc == 0);
1462         igt_assert(wait_for_suspended());
1463
1464         /* Move the new cursor. */
1465         rc = drmModeMoveCursor(drm_fd, crtc_id, 2, 2);
1466         igt_assert(rc == 0);
1467         igt_assert(wait_for_suspended());
1468
1469         /* Now set a new one without unsetting the previous one. */
1470         rc = drmModeSetCursor(drm_fd, crtc_id, cursor_fb1.gem_handle,
1471                               cursor_fb1.width, cursor_fb1.height);
1472         igt_assert(rc == 0);
1473         igt_assert(wait_for_suspended());
1474
1475         /* Cursor 3 was created with tiling and painted with a GTT mmap, so
1476          * hopefully it has some fences around it. */
1477         rc = drmModeRmFB(drm_fd, cursor_fb3.fb_id);
1478         igt_assert(rc == 0);
1479         gem_set_tiling(drm_fd, cursor_fb3.gem_handle, false, cursor_fb3.stride);
1480         igt_assert(wait_for_suspended());
1481
1482         rc = drmModeSetCursor(drm_fd, crtc_id, cursor_fb3.gem_handle,
1483                               cursor_fb3.width, cursor_fb3.height);
1484         igt_assert(rc == 0);
1485         igt_assert(wait_for_suspended());
1486
1487         /* Make sure nothing remains for the other tests. */
1488         rc = drmModeSetCursor(drm_fd, crtc_id, 0, 0, 0);
1489         igt_assert(rc == 0);
1490         igt_assert(wait_for_suspended());
1491 }
1492
1493 static enum plane_type get_plane_type(uint32_t plane_id)
1494 {
1495         int i;
1496         bool found;
1497         uint64_t prop_value;
1498         drmModePropertyPtr prop;
1499         const char *enum_name = NULL;
1500         enum plane_type type;
1501
1502         found = kmstest_get_property(drm_fd, plane_id, DRM_MODE_OBJECT_PLANE,
1503                                      "type", NULL, &prop_value, &prop);
1504         igt_assert(found);
1505
1506         igt_assert(prop->flags & DRM_MODE_PROP_ENUM);
1507         igt_assert(prop_value < prop->count_enums);
1508
1509         for (i = 0; i < prop->count_enums; i++) {
1510                 if (prop->enums[i].value == prop_value) {
1511                         enum_name = prop->enums[i].name;
1512                         break;
1513                 }
1514         }
1515         igt_assert(enum_name);
1516
1517         if (strcmp(enum_name, "Overlay") == 0)
1518                 type = PLANE_OVERLAY;
1519         else if (strcmp(enum_name, "Primary") == 0)
1520                 type = PLANE_PRIMARY;
1521         else if (strcmp(enum_name, "Cursor") == 0)
1522                 type = PLANE_CURSOR;
1523         else
1524                 igt_assert(0);
1525
1526         drmModeFreeProperty(prop);
1527
1528         return type;
1529 }
1530
1531 static void test_one_plane(bool dpms, uint32_t plane_id,
1532                            enum plane_type plane_type)
1533 {
1534         int rc;
1535         uint32_t plane_format, plane_w, plane_h;
1536         uint32_t crtc_id;
1537         struct igt_fb plane_fb1, plane_fb2;
1538         int32_t crtc_x = 0, crtc_y = 0;
1539         bool tiling;
1540
1541         disable_all_screens_and_wait(&ms_data);
1542
1543         igt_require(default_mode_params);
1544         crtc_id = default_mode_params->crtc_id;
1545
1546         switch (plane_type) {
1547         case PLANE_OVERLAY:
1548                 plane_format = DRM_FORMAT_XRGB8888;
1549                 plane_w = 64;
1550                 plane_h = 64;
1551                 tiling = true;
1552                 break;
1553         case PLANE_PRIMARY:
1554                 plane_format = DRM_FORMAT_XRGB8888;
1555                 plane_w = default_mode_params->mode->hdisplay;
1556                 plane_h = default_mode_params->mode->vdisplay;
1557                 tiling = true;
1558                 break;
1559         case PLANE_CURSOR:
1560                 plane_format = DRM_FORMAT_ARGB8888;
1561                 plane_w = 64;
1562                 plane_h = 64;
1563                 tiling = false;
1564                 break;
1565         default:
1566                 igt_assert(0);
1567                 break;
1568         }
1569
1570         igt_create_fb(drm_fd, plane_w, plane_h, plane_format, tiling,
1571                       &plane_fb1);
1572         igt_create_fb(drm_fd, plane_w, plane_h, plane_format, tiling,
1573                       &plane_fb2);
1574         fill_igt_fb(&plane_fb1, 0xFF00FFFF);
1575         fill_igt_fb(&plane_fb2, 0xFF00FF00);
1576
1577         set_mode_for_params_and_wait(default_mode_params);
1578
1579         rc = drmModeSetPlane(drm_fd, plane_id, crtc_id, plane_fb1.fb_id, 0,
1580                              0, 0, plane_fb1.width, plane_fb1.height,
1581                              0 << 16, 0 << 16, plane_fb1.width << 16,
1582                              plane_fb1.height << 16);
1583         igt_assert(rc == 0);
1584
1585         disable_or_dpms_all_screens_and_wait(&ms_data, dpms);
1586
1587         /* Just move the plane around. */
1588         if (plane_type != PLANE_PRIMARY) {
1589                 crtc_x++;
1590                 crtc_y++;
1591         }
1592         rc = drmModeSetPlane(drm_fd, plane_id, crtc_id, plane_fb1.fb_id, 0,
1593                              crtc_x, crtc_y, plane_fb1.width, plane_fb1.height,
1594                              0 << 16, 0 << 16, plane_fb1.width << 16,
1595                              plane_fb1.height << 16);
1596         igt_assert(rc == 0);
1597         igt_assert(wait_for_suspended());
1598
1599         /* Unset, then change the plane. */
1600         rc = drmModeSetPlane(drm_fd, plane_id, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
1601         igt_assert(rc == 0);
1602         igt_assert(wait_for_suspended());
1603
1604         rc = drmModeSetPlane(drm_fd, plane_id, crtc_id, plane_fb2.fb_id, 0,
1605                              crtc_x, crtc_y, plane_fb2.width, plane_fb2.height,
1606                              0 << 16, 0 << 16, plane_fb2.width << 16,
1607                              plane_fb2.height << 16);
1608         igt_assert(rc == 0);
1609         igt_assert(wait_for_suspended());
1610
1611         /* Now change the plane without unsetting first. */
1612         rc = drmModeSetPlane(drm_fd, plane_id, crtc_id, plane_fb1.fb_id, 0,
1613                              crtc_x, crtc_y, plane_fb1.width, plane_fb1.height,
1614                              0 << 16, 0 << 16, plane_fb1.width << 16,
1615                              plane_fb1.height << 16);
1616         igt_assert(rc == 0);
1617         igt_assert(wait_for_suspended());
1618
1619         /* Make sure nothing remains for the other tests. */
1620         rc = drmModeSetPlane(drm_fd, plane_id, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
1621         igt_assert(rc == 0);
1622         igt_assert(wait_for_suspended());
1623 }
1624
1625 /* This one also triggered WARNs on our driver at some point in time. */
1626 static void planes_subtest(bool universal, bool dpms)
1627 {
1628         int i, rc, planes_tested = 0;
1629         drmModePlaneResPtr planes;
1630
1631         if (universal) {
1632                 rc = drmSetClientCap(drm_fd, DRM_CLIENT_CAP_UNIVERSAL_PLANES,
1633                                      1);
1634                 igt_require(rc == 0);
1635         }
1636
1637         planes = drmModeGetPlaneResources(drm_fd);
1638         for (i = 0; i < planes->count_planes; i++) {
1639                 drmModePlanePtr plane;
1640
1641                 plane = drmModeGetPlane(drm_fd, planes->planes[i]);
1642                 igt_assert(plane);
1643
1644                 /* We just pick the first CRTC on the list, so we can test for
1645                  * 0x1 as the index. */
1646                 if (plane->possible_crtcs & 0x1) {
1647                         enum plane_type type;
1648
1649                         type = universal ? get_plane_type(plane->plane_id) :
1650                                            PLANE_OVERLAY;
1651                         test_one_plane(dpms, plane->plane_id, type);
1652                         planes_tested++;
1653                 }
1654                 drmModeFreePlane(plane);
1655         }
1656         drmModeFreePlaneResources(planes);
1657
1658         if (universal) {
1659                 rc = drmSetClientCap(drm_fd, DRM_CLIENT_CAP_UNIVERSAL_PLANES, 0);
1660                 igt_assert(rc == 0);
1661
1662                 igt_assert(planes_tested >= 3);
1663         } else {
1664                 igt_assert(planes_tested >= 1);
1665         }
1666 }
1667
1668 static void fences_subtest(bool dpms)
1669 {
1670         int i;
1671         uint32_t *buf_ptr;
1672         uint32_t tiling = false, swizzle;
1673         struct modeset_params params;
1674
1675         disable_all_screens_and_wait(&ms_data);
1676
1677         igt_require(default_mode_params);
1678         params.crtc_id = default_mode_params->crtc_id;
1679         params.connector_id = default_mode_params->connector_id;
1680         params.mode = default_mode_params->mode;
1681         igt_create_fb(drm_fd, params.mode->hdisplay, params.mode->vdisplay,
1682                       DRM_FORMAT_XRGB8888, true, &params.fb);
1683
1684         /* Even though we passed "true" as the tiling argument, double-check
1685          * that the fb is really tiled. */
1686         gem_get_tiling(drm_fd, params.fb.gem_handle, &tiling, &swizzle);
1687         igt_assert(tiling);
1688
1689         buf_ptr = gem_mmap__gtt(drm_fd, params.fb.gem_handle,
1690                                 params.fb.size, PROT_WRITE | PROT_READ);
1691         for (i = 0; i < params.fb.size/sizeof(uint32_t); i++)
1692                 buf_ptr[i] = i;
1693
1694         set_mode_for_params_and_wait(&params);
1695
1696         disable_or_dpms_all_screens_and_wait(&ms_data, dpms);
1697
1698         for (i = 0; i < params.fb.size/sizeof(uint32_t); i++)
1699                 igt_assert_eq(buf_ptr[i], i);
1700         igt_assert(wait_for_suspended());
1701
1702         if (dpms) {
1703                 drmModeConnectorPtr c = NULL;
1704
1705                 for (i = 0; i < ms_data.res->count_connectors; i++)
1706                         if (ms_data.connectors[i]->connector_id ==
1707                             params.connector_id)
1708                                 c = ms_data.connectors[i];
1709                 igt_assert(c);
1710
1711                 kmstest_set_connector_dpms(drm_fd, c, DRM_MODE_DPMS_ON);
1712         } else {
1713                 set_mode_for_params(&params);
1714         }
1715         igt_assert(wait_for_active());
1716
1717         for (i = 0; i < params.fb.size/sizeof(uint32_t); i++)
1718                 igt_assert_eq(buf_ptr[i], i);
1719
1720         igt_assert(munmap(buf_ptr, params.fb.size) == 0);
1721 }
1722
1723 int rounds = 50;
1724 bool stay = false;
1725
1726 static int opt_handler(int opt, int opt_index)
1727 {
1728         switch (opt) {
1729         case 'q':
1730                 rounds = 10;
1731                 break;
1732         case 's':
1733                 stay = true;
1734                 break;
1735         default:
1736                 igt_assert(0);
1737         }
1738
1739         return 0;
1740 }
1741
1742 int main(int argc, char *argv[])
1743 {
1744         const char *help_str =
1745                "  --quick\t\tMake the stress-tests not stressful, for quick regression testing.\n"
1746                "  --stay\t\tDisable all screen and try to go into runtime pm. Useful for debugging.";
1747         static struct option long_options[] = {
1748                 {"quick", 0, 0, 'q'},
1749                 {"stay", 0, 0, 's'},
1750                 { 0, 0, 0, 0 }
1751         };
1752
1753         igt_subtest_init_parse_opts(argc, argv, "", long_options,
1754                                     help_str, opt_handler);
1755
1756         /* Skip instead of failing in case the machine is not prepared to reach
1757          * PC8+. We don't want bug reports from cases where the machine is just
1758          * not properly configured. */
1759         igt_fixture
1760                 setup_environment();
1761
1762         if (stay)
1763                 igt_subtest("stay")
1764                         stay_subtest();
1765
1766         /* Essential things */
1767         igt_subtest("rte")
1768                 basic_subtest();
1769         igt_subtest("drm-resources-equal")
1770                 drm_resources_equal_subtest();
1771         igt_subtest("pci-d3-state")
1772                 pci_d3_state_subtest();
1773
1774         /* Basic modeset */
1775         igt_subtest("modeset-lpsp")
1776                 modeset_subtest(SCREEN_TYPE_LPSP, 1, WAIT_STATUS);
1777         igt_subtest("modeset-non-lpsp")
1778                 modeset_subtest(SCREEN_TYPE_NON_LPSP, 1, WAIT_STATUS);
1779         igt_subtest("dpms-lpsp")
1780                 modeset_subtest(SCREEN_TYPE_LPSP, 1, WAIT_STATUS | USE_DPMS);
1781         igt_subtest("dpms-non-lpsp")
1782                 modeset_subtest(SCREEN_TYPE_NON_LPSP, 1, WAIT_STATUS | USE_DPMS);
1783
1784         /* GEM */
1785         igt_subtest("gem-mmap-cpu")
1786                 gem_mmap_subtest(false);
1787         igt_subtest("gem-mmap-gtt")
1788                 gem_mmap_subtest(true);
1789         igt_subtest("gem-pread")
1790                 gem_pread_subtest();
1791         igt_subtest("gem-execbuf")
1792                 gem_execbuf_subtest();
1793         igt_subtest("gem-idle")
1794                 gem_idle_subtest();
1795
1796         /* Planes and cursors */
1797         igt_subtest("cursor")
1798                 cursor_subtest(false);
1799         igt_subtest("cursor-dpms")
1800                 cursor_subtest(true);
1801         igt_subtest("legacy-planes")
1802                 planes_subtest(false, false);
1803         igt_subtest("legacy-planes-dpms")
1804                 planes_subtest(false, true);
1805         igt_subtest("universal-planes")
1806                 planes_subtest(true, false);
1807         igt_subtest("universal-planes-dpms")
1808                 planes_subtest(true, true);
1809
1810         /* Misc */
1811         igt_subtest("reg-read-ioctl")
1812                 reg_read_ioctl_subtest();
1813         igt_subtest("i2c")
1814                 i2c_subtest();
1815         igt_subtest("pc8-residency")
1816                 pc8_residency_subtest();
1817         igt_subtest("debugfs-read")
1818                 debugfs_read_subtest();
1819         igt_subtest("debugfs-forcewake-user")
1820                 debugfs_forcewake_user_subtest();
1821         igt_subtest("sysfs-read")
1822                 sysfs_read_subtest();
1823         igt_subtest("dpms-mode-unset-lpsp")
1824                 dpms_mode_unset_subtest(SCREEN_TYPE_LPSP);
1825         igt_subtest("dpms-mode-unset-non-lpsp")
1826                 dpms_mode_unset_subtest(SCREEN_TYPE_NON_LPSP);
1827         igt_subtest("fences")
1828                 fences_subtest(false);
1829         igt_subtest("fences-dpms")
1830                 fences_subtest(true);
1831
1832         /* Modeset stress */
1833         igt_subtest("modeset-lpsp-stress")
1834                 modeset_subtest(SCREEN_TYPE_LPSP, rounds, WAIT_STATUS);
1835         igt_subtest("modeset-non-lpsp-stress")
1836                 modeset_subtest(SCREEN_TYPE_NON_LPSP, rounds, WAIT_STATUS);
1837         igt_subtest("modeset-lpsp-stress-no-wait")
1838                 modeset_subtest(SCREEN_TYPE_LPSP, rounds, DONT_WAIT);
1839         igt_subtest("modeset-non-lpsp-stress-no-wait")
1840                 modeset_subtest(SCREEN_TYPE_NON_LPSP, rounds, DONT_WAIT);
1841         igt_subtest("modeset-pc8-residency-stress")
1842                 modeset_subtest(SCREEN_TYPE_ANY, rounds, WAIT_PC8_RES);
1843         igt_subtest("modeset-stress-extra-wait")
1844                 modeset_subtest(SCREEN_TYPE_ANY, rounds,
1845                                 WAIT_STATUS | WAIT_EXTRA);
1846
1847         /* System suspend */
1848         igt_subtest("system-suspend")
1849                 system_suspend_subtest();
1850
1851         /* GEM stress */
1852         igt_subtest("gem-execbuf-stress")
1853                 gem_execbuf_stress_subtest(rounds, WAIT_STATUS);
1854         igt_subtest("gem-execbuf-stress-pc8")
1855                 gem_execbuf_stress_subtest(rounds, WAIT_PC8_RES);
1856         igt_subtest("gem-execbuf-stress-extra-wait")
1857                 gem_execbuf_stress_subtest(rounds, WAIT_STATUS | WAIT_EXTRA);
1858
1859         igt_fixture
1860                 teardown_environment();
1861
1862         igt_exit();
1863 }