2 * Copyright © 2014 Intel Corporation
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11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Chris Wilson <chris@chris-wilson.co.uk>
29 * Testcase: Exercise a suspect workaround required for FORCEWAKE_MT
33 #include <sys/types.h>
39 #include "i915_pciids.h"
41 #include "intel_gpu_tools.h"
43 #define FORCEWAKE_MT 0xa188
52 static const struct pci_id_match match[] = {
53 INTEL_IVB_D_IDS(NULL),
54 INTEL_IVB_M_IDS(NULL),
56 INTEL_HSW_D_IDS(NULL),
57 INTEL_HSW_M_IDS(NULL),
62 static struct pci_device *__igfx_get(void)
64 struct pci_device *dev;
66 if (pci_system_init())
69 dev = pci_device_find_by_slot(0, 0, 2, 0);
70 if (dev == NULL || dev->vendor_id != 0x8086) {
71 struct pci_device_iterator *iter;
73 iter = pci_id_match_iterator_create(match);
77 dev = pci_device_next(iter);
78 pci_iterator_destroy(iter);
84 static void *igfx_get_mmio(void)
86 struct pci_device *pci = __igfx_get();
89 igt_skip_on(pci == NULL);
90 igt_skip_on(intel_gen(pci->device_id) != 7);
92 error = pci_device_probe(pci);
93 igt_assert(error == 0);
95 error = pci_device_map_range(pci,
96 pci->regions[0].base_addr,
98 PCI_DEV_MAP_FLAG_WRITABLE,
100 igt_assert(error == 0);
101 igt_assert(mmio != NULL);
106 static void *thread(void *arg)
108 struct thread *t = arg;
109 uint32_t *forcewake_mt = (uint32_t *)((char *)t->mmio + FORCEWAKE_MT);
110 uint32_t bit = 1 << t->bit;
113 *forcewake_mt = bit << 16 | bit;
114 igt_assert(*forcewake_mt & bit);
115 *forcewake_mt = bit << 16;
116 igt_assert((*forcewake_mt & bit) == 0);
122 #define MI_LOAD_REGISTER_IMM (0x22<<23)
123 #define MI_STORE_REGISTER_MEM (0x24<<23| 1<<22)
130 t[0].fd = drm_open_any();
131 t[0].mmio = igfx_get_mmio();
133 for (i = 2; i < 16; i++) {
136 pthread_create(&t[i].thread, NULL, thread, &t[i]);
141 for (i = 0; i < 1000; i++) {
142 struct drm_i915_gem_execbuffer2 execbuf;
143 struct drm_i915_gem_exec_object2 exec;
144 struct drm_i915_gem_relocation_entry reloc[2];
146 MI_LOAD_REGISTER_IMM | 1,
149 MI_STORE_REGISTER_MEM | 1,
152 MI_LOAD_REGISTER_IMM | 1,
155 MI_STORE_REGISTER_MEM | 1,
162 memset(&exec, 0, sizeof(exec));
163 exec.handle = gem_create(t[0].fd, 4096);
164 exec.relocation_count = 2;
165 exec.relocs_ptr = (uintptr_t)reloc;
166 //exec.flags = EXEC_OBJECT_NEEDS_GTT;
167 gem_write(t[0].fd, exec.handle, 0, b, sizeof(b));
169 reloc[0].offset = 5 * sizeof(uint32_t);
170 reloc[0].delta = 5 * sizeof(uint32_t);
171 reloc[0].target_handle = exec.handle;
172 reloc[0].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
173 reloc[0].write_domain = 0;
174 reloc[0].presumed_offset = 0;
176 reloc[1].offset = 11 * sizeof(uint32_t);
177 reloc[1].delta = 11 * sizeof(uint32_t);
178 reloc[1].target_handle = exec.handle;
179 reloc[1].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
180 reloc[1].write_domain = 0;
181 reloc[1].presumed_offset = 0;
183 memset(&execbuf, 0, sizeof(execbuf));
184 execbuf.buffers_ptr = (uintptr_t)&exec;
185 execbuf.buffer_count = 1;
186 execbuf.batch_len = sizeof(b);
187 execbuf.flags = I915_EXEC_SECURE;
189 gem_execbuf(t[0].fd, &execbuf);
190 gem_sync(t[0].fd, exec.handle);
191 gem_read(t[0].fd, exec.handle, 0, b, sizeof(b));
192 gem_close(t[0].fd, exec.handle);
194 printf("[%d]={ %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x }\n",
195 i, b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7], b[8], b[9], b[10], b[11], b[12]);
197 igt_assert(b[5] & 2);
198 igt_assert((b[11] & 2) == 0);