2 * Copyright © 2014 Intel Corporation
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11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Chris Wilson <chris@chris-wilson.co.uk>
29 * Testcase: Exercise a suspect workaround required for FORCEWAKE_MT
33 #include <sys/types.h>
38 #include "ioctl_wrappers.h"
39 #include "i915_pciids.h"
42 #include "intel_chipset.h"
44 #define FORCEWAKE_MT 0xa188
53 static const struct pci_id_match match[] = {
54 INTEL_IVB_D_IDS(NULL),
55 INTEL_IVB_M_IDS(NULL),
57 INTEL_HSW_D_IDS(NULL),
58 INTEL_HSW_M_IDS(NULL),
63 static struct pci_device *__igfx_get(void)
65 struct pci_device *dev;
67 if (pci_system_init())
70 dev = pci_device_find_by_slot(0, 0, 2, 0);
71 if (dev == NULL || dev->vendor_id != 0x8086) {
72 struct pci_device_iterator *iter;
74 iter = pci_id_match_iterator_create(match);
78 dev = pci_device_next(iter);
79 pci_iterator_destroy(iter);
85 static void *igfx_get_mmio(void)
87 struct pci_device *pci = __igfx_get();
90 igt_skip_on(pci == NULL);
91 igt_skip_on(intel_gen(pci->device_id) != 7);
93 error = pci_device_probe(pci);
94 igt_assert(error == 0);
96 error = pci_device_map_range(pci,
97 pci->regions[0].base_addr,
99 PCI_DEV_MAP_FLAG_WRITABLE,
101 igt_assert(error == 0);
102 igt_assert(mmio != NULL);
107 static void *thread(void *arg)
109 struct thread *t = arg;
110 uint32_t *forcewake_mt = (uint32_t *)((char *)t->mmio + FORCEWAKE_MT);
111 uint32_t bit = 1 << t->bit;
114 *forcewake_mt = bit << 16 | bit;
115 igt_assert(*forcewake_mt & bit);
116 *forcewake_mt = bit << 16;
117 igt_assert((*forcewake_mt & bit) == 0);
123 #define MI_LOAD_REGISTER_IMM (0x22<<23)
124 #define MI_STORE_REGISTER_MEM (0x24<<23)
131 t[0].fd = drm_open_any();
132 t[0].mmio = igfx_get_mmio();
134 for (i = 2; i < 16; i++) {
137 pthread_create(&t[i].thread, NULL, thread, &t[i]);
142 for (i = 0; i < 1000; i++) {
144 struct drm_i915_gem_execbuffer2 execbuf;
145 struct drm_i915_gem_exec_object2 exec[2];
146 struct drm_i915_gem_relocation_entry reloc[2];
148 MI_LOAD_REGISTER_IMM | 1,
151 MI_STORE_REGISTER_MEM | 1,
154 MI_LOAD_REGISTER_IMM | 1,
157 MI_STORE_REGISTER_MEM | 1,
159 1 * sizeof(uint32_t), // to be patched
164 memset(exec, 0, sizeof(exec));
165 exec[1].handle = gem_create(t[0].fd, 4096);
166 exec[1].relocation_count = 2;
167 exec[1].relocs_ptr = (uintptr_t)reloc;
168 gem_write(t[0].fd, exec[1].handle, 0, b, sizeof(b));
169 exec[0].handle = gem_create(t[0].fd, 4096);
171 reloc[0].offset = 5 * sizeof(uint32_t);
173 reloc[0].target_handle = exec[0].handle;
174 reloc[0].read_domains = I915_GEM_DOMAIN_RENDER;
175 reloc[0].write_domain = I915_GEM_DOMAIN_RENDER;
176 reloc[0].presumed_offset = 0;
178 reloc[1].offset = 11 * sizeof(uint32_t);
179 reloc[1].delta = 1 * sizeof(uint32_t);
180 reloc[1].target_handle = exec[0].handle;
181 reloc[1].read_domains = I915_GEM_DOMAIN_RENDER;
182 reloc[1].write_domain = I915_GEM_DOMAIN_RENDER;
183 reloc[1].presumed_offset = 0;
185 memset(&execbuf, 0, sizeof(execbuf));
186 execbuf.buffers_ptr = (uintptr_t)&exec;
187 execbuf.buffer_count = 2;
188 execbuf.batch_len = sizeof(b);
189 execbuf.flags = I915_EXEC_SECURE;
191 gem_execbuf(t[0].fd, &execbuf);
192 gem_sync(t[0].fd, exec[1].handle);
194 p = gem_mmap(t[0].fd, exec[0].handle, 4096, PROT_READ);
196 igt_info("[%d]={ %08x %08x }\n", i, p[0], p[1]);
197 igt_assert(p[0] & 2);
198 igt_assert((p[1] & 2) == 0);
201 gem_close(t[0].fd, exec[0].handle);
202 gem_close(t[0].fd, exec[1].handle);