2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Chris Wilson <chris@chris-wilson.co.uk>
28 /** @file gen3_linear_render_blits.c
30 * This is a test of doing many blits, with a working set
31 * larger than the aperture size.
33 * The goal is to simply ensure the basics work.
46 #include <sys/ioctl.h>
50 #include "intel_gpu_tools.h"
58 static inline uint32_t pack_float(float f)
68 static uint32_t gem_create(int fd, int size)
70 struct drm_i915_gem_create create;
74 (void)drmIoctl(fd, DRM_IOCTL_I915_GEM_CREATE, &create);
75 assert(create.handle);
80 static void gem_close(int fd, uint32_t handle)
82 struct drm_gem_close close;
85 close.handle = handle;
86 ret = drmIoctl(fd, DRM_IOCTL_GEM_CLOSE, &close);
91 gem_aperture_size(int fd)
93 struct drm_i915_gem_get_aperture aperture;
95 aperture.aper_size = 512*1024*1024;
96 (void)drmIoctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
97 return aperture.aper_size;
101 gem_write(int fd, uint32_t handle, int offset, int size, const void *buf)
103 struct drm_i915_gem_pwrite pwrite;
106 pwrite.handle = handle;
107 pwrite.offset = offset;
109 pwrite.data_ptr = (uintptr_t)buf;
110 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_PWRITE, &pwrite);
114 static uint32_t fill_reloc(struct drm_i915_gem_relocation_entry *reloc,
117 uint32_t read_domain,
118 uint32_t write_domain)
120 reloc->target_handle = handle;
122 reloc->offset = offset * sizeof(uint32_t);
123 reloc->presumed_offset = 0;
124 reloc->read_domains = read_domain;
125 reloc->write_domain = write_domain;
127 return reloc->presumed_offset + reloc->delta;
131 copy(int fd, uint32_t dst, uint32_t src)
133 uint32_t batch[1024], *b = batch;
134 struct drm_i915_gem_relocation_entry reloc[2], *r = reloc;
135 struct drm_i915_gem_exec_object2 obj[3];
136 struct drm_i915_gem_execbuffer2 exec;
140 /* invariant state */
141 *b++ = (_3DSTATE_AA_CMD |
142 AA_LINE_ECAAR_WIDTH_ENABLE |
143 AA_LINE_ECAAR_WIDTH_1_0 |
144 AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
145 *b++ = (_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD |
147 IAB_MODIFY_FUNC | (BLENDFUNC_ADD << IAB_FUNC_SHIFT) |
148 IAB_MODIFY_SRC_FACTOR | (BLENDFACT_ONE <<
149 IAB_SRC_FACTOR_SHIFT) |
150 IAB_MODIFY_DST_FACTOR | (BLENDFACT_ZERO <<
151 IAB_DST_FACTOR_SHIFT));
152 *b++ = (_3DSTATE_DFLT_DIFFUSE_CMD);
154 *b++ = (_3DSTATE_DFLT_SPEC_CMD);
156 *b++ = (_3DSTATE_DFLT_Z_CMD);
158 *b++ = (_3DSTATE_COORD_SET_BINDINGS |
164 CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
165 *b++ = (_3DSTATE_RASTER_RULES_CMD |
166 ENABLE_POINT_RASTER_RULE |
167 OGL_POINT_RASTER_RULE |
168 ENABLE_LINE_STRIP_PROVOKE_VRTX |
169 ENABLE_TRI_FAN_PROVOKE_VRTX |
170 LINE_STRIP_PROVOKE_VRTX(1) |
171 TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D | TEXKILL_4D);
172 *b++ = (_3DSTATE_MODES_4_CMD |
173 ENABLE_LOGIC_OP_FUNC | LOGIC_OP_FUNC(LOGICOP_COPY) |
174 ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff) |
175 ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff));
176 *b++ = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | I1_LOAD_S(4) | I1_LOAD_S(5) | 2);
177 *b++ = (0x00000000); /* Disable texture coordinate wrap-shortest */
178 *b++ = ((1 << S4_POINT_WIDTH_SHIFT) |
182 *b++ = (0x00000000); /* Stencil. */
183 *b++ = (_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
184 *b++ = (_3DSTATE_SCISSOR_RECT_0_CMD);
187 *b++ = (_3DSTATE_DEPTH_SUBRECT_DISABLE);
188 *b++ = (_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
190 *b++ = (_3DSTATE_STIPPLE);
192 *b++ = (_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0);
196 *b++ = (_3DSTATE_MAP_STATE | (3 * TEX_COUNT));
197 *b++ = ((1 << TEX_COUNT) - 1);
198 *b = fill_reloc(r++, b-batch, src, I915_GEM_DOMAIN_SAMPLER, 0); b++;
199 *b++ = (MAPSURF_32BIT | MT_32BIT_ARGB8888 |
200 MS3_TILED_SURFACE | MS3_TILE_WALK |
201 (HEIGHT - 1) << MS3_HEIGHT_SHIFT |
202 (WIDTH - 1) << MS3_WIDTH_SHIFT);
203 *b++ = ((WIDTH-1) << MS4_PITCH_SHIFT);
205 *b++ = (_3DSTATE_SAMPLER_STATE | (3 * TEX_COUNT));
206 *b++ = ((1 << TEX_COUNT) - 1);
207 *b++ = (MIPFILTER_NONE << SS2_MIP_FILTER_SHIFT |
208 FILTER_NEAREST << SS2_MAG_FILTER_SHIFT |
209 FILTER_NEAREST << SS2_MIN_FILTER_SHIFT);
210 *b++ = (TEXCOORDMODE_WRAP << SS3_TCX_ADDR_MODE_SHIFT |
211 TEXCOORDMODE_WRAP << SS3_TCY_ADDR_MODE_SHIFT |
212 0 << SS3_TEXTUREMAP_INDEX_SHIFT);
215 /* render target state */
216 *b++ = (_3DSTATE_BUF_INFO_CMD);
217 *b++ = (BUF_3D_ID_COLOR_BACK | BUF_3D_TILED_SURFACE | BUF_3D_TILE_WALK_Y | WIDTH*4);
218 *b = fill_reloc(r++, b-batch, dst,
219 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
222 *b++ = (_3DSTATE_DST_BUF_VARS_CMD);
223 *b++ = (COLR_BUF_ARGB8888 |
224 DSTORG_HORT_BIAS(0x8) |
225 DSTORG_VERT_BIAS(0x8));
227 /* draw rect is unconditional */
228 *b++ = (_3DSTATE_DRAW_RECT_CMD);
230 *b++ = (0x00000000); /* ymin, xmin */
231 *b++ = (DRAW_YMAX(HEIGHT - 1) |
232 DRAW_XMAX(WIDTH - 1));
233 /* yorig, xorig (relate to color buffer?) */
237 *b++ = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(1) | I1_LOAD_S(2) | I1_LOAD_S(6) | 2);
238 *b++ = ((4 << S1_VERTEX_WIDTH_SHIFT) | (4 << S1_VERTEX_PITCH_SHIFT));
239 *b++ = (~S2_TEXCOORD_FMT(0, TEXCOORDFMT_NOT_PRESENT) |
240 S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D));
241 *b++ = (S6_CBUF_BLEND_ENABLE | S6_COLOR_WRITE_ENABLE |
242 BLENDFUNC_ADD << S6_CBUF_BLEND_FUNC_SHIFT |
243 BLENDFACT_ONE << S6_CBUF_SRC_BLEND_FACT_SHIFT |
244 BLENDFACT_ZERO << S6_CBUF_DST_BLEND_FACT_SHIFT);
247 *b++ = (_3DSTATE_PIXEL_SHADER_PROGRAM | (1 + 3*3 - 2));
250 REG_TYPE(FS_T0) << D0_TYPE_SHIFT |
251 REG_NR(FS_T0) << D0_NR_SHIFT |
252 ((REG_TYPE(FS_T0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0));
257 (REG_TYPE(FS_S0) << D0_TYPE_SHIFT) |
258 (REG_NR(FS_S0) << D0_NR_SHIFT) |
259 ((REG_TYPE(FS_S0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0));
262 /* texld(FS_OC, FS_S0, FS_T0 */
264 (REG_TYPE(FS_OC) << T0_DEST_TYPE_SHIFT) |
265 (REG_NR(FS_OC) << T0_DEST_NR_SHIFT) |
266 (REG_NR(FS_S0) << T0_SAMPLER_NR_SHIFT));
267 *b++ = ((REG_TYPE(FS_T0) << T1_ADDRESS_REG_TYPE_SHIFT) |
268 (REG_NR(FS_T0) << T1_ADDRESS_REG_NR_SHIFT));
271 *b++ = (PRIM3D_RECTLIST | (3*4 - 1));
272 *b++ = pack_float(WIDTH);
273 *b++ = pack_float(HEIGHT);
274 *b++ = pack_float(WIDTH);
275 *b++ = pack_float(HEIGHT);
277 *b++ = pack_float(0);
278 *b++ = pack_float(HEIGHT);
279 *b++ = pack_float(0);
280 *b++ = pack_float(HEIGHT);
282 *b++ = pack_float(0);
283 *b++ = pack_float(0);
284 *b++ = pack_float(0);
285 *b++ = pack_float(0);
287 *b++ = MI_BATCH_BUFFER_END;
291 assert(b - batch <= 1024);
292 handle = gem_create(fd, 4096);
293 gem_write(fd, handle, 0, (b-batch)*sizeof(batch[0]), batch);
295 assert(r-reloc == 2);
298 obj[0].relocation_count = 0;
299 obj[0].relocs_ptr = 0;
300 obj[0].alignment = 0;
307 obj[1].relocation_count = 0;
308 obj[1].relocs_ptr = 0;
309 obj[1].alignment = 0;
315 obj[2].handle = handle;
316 obj[2].relocation_count = 2;
317 obj[2].relocs_ptr = (uintptr_t)reloc;
318 obj[2].alignment = 0;
321 obj[2].rsvd1 = obj[2].rsvd2 = 0;
323 exec.buffers_ptr = (uintptr_t)obj;
324 exec.buffer_count = 3;
325 exec.batch_start_offset = 0;
326 exec.batch_len = (b-batch)*sizeof(batch[0]);
327 exec.DR1 = exec.DR4 = 0;
328 exec.num_cliprects = 0;
329 exec.cliprects_ptr = 0;
331 exec.rsvd1 = exec.rsvd2 = 0;
333 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
334 while (ret && errno == EBUSY) {
335 drmCommandNone(fd, DRM_I915_GEM_THROTTLE);
336 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
340 gem_close(fd, handle);
343 static void *gem_mmap(int fd, uint32_t handle, int size, int prot)
345 struct drm_i915_gem_mmap_gtt mmap_arg;
348 mmap_arg.handle = handle;
349 if (drmIoctl(fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &mmap_arg)) {
354 ptr = mmap(0, size, prot, MAP_SHARED, fd, mmap_arg.offset);
355 if (ptr == MAP_FAILED) {
363 static void gem_set_tiling(int fd, uint32_t handle, int tiling, int stride)
365 struct drm_i915_gem_set_tiling set_tiling;
369 set_tiling.handle = handle;
370 set_tiling.tiling_mode = tiling;
371 set_tiling.stride = stride;
373 ret = ioctl(fd, DRM_IOCTL_I915_GEM_SET_TILING, &set_tiling);
374 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
376 assert(set_tiling.tiling_mode == tiling);
380 create_bo(int fd, uint32_t val)
386 handle = gem_create(fd, WIDTH*HEIGHT*4);
387 gem_set_tiling(fd, handle, I915_TILING_Y, WIDTH*4);
389 /* Fill the BO with dwords starting at val */
390 v = gem_mmap(fd, handle, WIDTH*HEIGHT*4, PROT_READ | PROT_WRITE);
391 for (i = 0; i < WIDTH*HEIGHT; i++)
393 munmap(v, WIDTH*HEIGHT*4);
399 check_bo(int fd, uint32_t handle, uint32_t val)
404 v = gem_mmap(fd, handle, WIDTH*HEIGHT*4, PROT_READ);
405 for (i = 0; i < WIDTH*HEIGHT; i++) {
407 fprintf(stderr, "Expected 0x%08x, found 0x%08x "
408 "at offset 0x%08x\n",
414 munmap(v, WIDTH*HEIGHT*4);
417 int main(int argc, char **argv)
419 uint32_t *handle, *start_val;
427 count = atoi(argv[1]);
429 count = 3 * gem_aperture_size(fd) / (1024*1024) / 2;
430 printf("Using %d 1MiB buffers\n", count);
432 handle = malloc(sizeof(uint32_t)*count*2);
433 start_val = handle + count;
435 for (i = 0; i < count; i++) {
436 handle[i] = create_bo(fd, start);
437 start_val[i] = start;
438 start += 1024 * 1024 / 4;
441 printf("Verifying initialisation..."); fflush(stdout);
442 for (i = 0; i < count; i++)
443 check_bo(fd, handle[i], start_val[i]);
446 printf("Cyclic blits, forward..."); fflush(stdout);
447 for (i = 0; i < count * 32; i++) {
449 int dst = (i + 1) % count;
451 copy(fd, handle[dst], handle[src]);
452 start_val[dst] = start_val[src];
454 printf("verifying..."); fflush(stdout);
455 for (i = 0; i < count; i++)
456 check_bo(fd, handle[i], start_val[i]);
459 printf("Cyclic blits, backward..."); fflush(stdout);
460 for (i = 0; i < count * 32; i++) {
461 int src = (i + 1) % count;
464 copy(fd, handle[dst], handle[src]);
465 start_val[dst] = start_val[src];
467 printf("verifying..."); fflush(stdout);
468 for (i = 0; i < count; i++)
469 check_bo(fd, handle[i], start_val[i]);
472 printf("Random blits..."); fflush(stdout);
473 for (i = 0; i < count * 32; i++) {
474 int src = random() % count;
475 int dst = random() % count;
478 dst = random() % count;
480 copy(fd, handle[dst], handle[src]);
481 start_val[dst] = start_val[src];
483 printf("verifying..."); fflush(stdout);
484 for (i = 0; i < count; i++)
485 check_bo(fd, handle[i], start_val[i]);