2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Chris Wilson <chris@chris-wilson.co.uk>
28 /** @file gen3_linear_render_blits.c
30 * This is a test of doing many blits, with a working set
31 * larger than the aperture size.
33 * The goal is to simply ensure the basics work.
44 #include <sys/ioctl.h>
46 #include "ioctl_wrappers.h"
49 #include "intel_chipset.h"
57 static inline uint32_t pack_float(float f)
67 static uint32_t fill_reloc(struct drm_i915_gem_relocation_entry *reloc,
71 uint32_t write_domain)
73 reloc->target_handle = handle;
75 reloc->offset = offset * sizeof(uint32_t);
76 reloc->presumed_offset = 0;
77 reloc->read_domains = read_domain;
78 reloc->write_domain = write_domain;
80 return reloc->presumed_offset + reloc->delta;
84 copy(int fd, uint32_t dst, uint32_t src)
86 uint32_t batch[1024], *b = batch;
87 struct drm_i915_gem_relocation_entry reloc[2], *r = reloc;
88 struct drm_i915_gem_exec_object2 obj[3];
89 struct drm_i915_gem_execbuffer2 exec;
94 *b++ = (_3DSTATE_AA_CMD |
95 AA_LINE_ECAAR_WIDTH_ENABLE |
96 AA_LINE_ECAAR_WIDTH_1_0 |
97 AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
98 *b++ = (_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD |
100 IAB_MODIFY_FUNC | (BLENDFUNC_ADD << IAB_FUNC_SHIFT) |
101 IAB_MODIFY_SRC_FACTOR | (BLENDFACT_ONE <<
102 IAB_SRC_FACTOR_SHIFT) |
103 IAB_MODIFY_DST_FACTOR | (BLENDFACT_ZERO <<
104 IAB_DST_FACTOR_SHIFT));
105 *b++ = (_3DSTATE_DFLT_DIFFUSE_CMD);
107 *b++ = (_3DSTATE_DFLT_SPEC_CMD);
109 *b++ = (_3DSTATE_DFLT_Z_CMD);
111 *b++ = (_3DSTATE_COORD_SET_BINDINGS |
117 CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
118 *b++ = (_3DSTATE_RASTER_RULES_CMD |
119 ENABLE_POINT_RASTER_RULE |
120 OGL_POINT_RASTER_RULE |
121 ENABLE_LINE_STRIP_PROVOKE_VRTX |
122 ENABLE_TRI_FAN_PROVOKE_VRTX |
123 LINE_STRIP_PROVOKE_VRTX(1) |
124 TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D | TEXKILL_4D);
125 *b++ = (_3DSTATE_MODES_4_CMD |
126 ENABLE_LOGIC_OP_FUNC | LOGIC_OP_FUNC(LOGICOP_COPY) |
127 ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff) |
128 ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff));
129 *b++ = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | I1_LOAD_S(4) | I1_LOAD_S(5) | 2);
130 *b++ = (0x00000000); /* Disable texture coordinate wrap-shortest */
131 *b++ = ((1 << S4_POINT_WIDTH_SHIFT) |
135 *b++ = (0x00000000); /* Stencil. */
136 *b++ = (_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
137 *b++ = (_3DSTATE_SCISSOR_RECT_0_CMD);
140 *b++ = (_3DSTATE_DEPTH_SUBRECT_DISABLE);
141 *b++ = (_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
143 *b++ = (_3DSTATE_STIPPLE);
145 *b++ = (_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0);
149 *b++ = (_3DSTATE_MAP_STATE | (3 * TEX_COUNT));
150 *b++ = ((1 << TEX_COUNT) - 1);
151 *b = fill_reloc(r++, b-batch, src, I915_GEM_DOMAIN_SAMPLER, 0); b++;
152 *b++ = (MAPSURF_32BIT | MT_32BIT_ARGB8888 |
153 MS3_TILED_SURFACE | MS3_TILE_WALK |
154 (HEIGHT - 1) << MS3_HEIGHT_SHIFT |
155 (WIDTH - 1) << MS3_WIDTH_SHIFT);
156 *b++ = ((WIDTH-1) << MS4_PITCH_SHIFT);
158 *b++ = (_3DSTATE_SAMPLER_STATE | (3 * TEX_COUNT));
159 *b++ = ((1 << TEX_COUNT) - 1);
160 *b++ = (MIPFILTER_NONE << SS2_MIP_FILTER_SHIFT |
161 FILTER_NEAREST << SS2_MAG_FILTER_SHIFT |
162 FILTER_NEAREST << SS2_MIN_FILTER_SHIFT);
163 *b++ = (TEXCOORDMODE_WRAP << SS3_TCX_ADDR_MODE_SHIFT |
164 TEXCOORDMODE_WRAP << SS3_TCY_ADDR_MODE_SHIFT |
165 0 << SS3_TEXTUREMAP_INDEX_SHIFT);
168 /* render target state */
169 *b++ = (_3DSTATE_BUF_INFO_CMD);
170 *b++ = (BUF_3D_ID_COLOR_BACK | BUF_3D_TILED_SURFACE | BUF_3D_TILE_WALK_Y | WIDTH*4);
171 *b = fill_reloc(r++, b-batch, dst,
172 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
175 *b++ = (_3DSTATE_DST_BUF_VARS_CMD);
176 *b++ = (COLR_BUF_ARGB8888 |
177 DSTORG_HORT_BIAS(0x8) |
178 DSTORG_VERT_BIAS(0x8));
180 /* draw rect is unconditional */
181 *b++ = (_3DSTATE_DRAW_RECT_CMD);
183 *b++ = (0x00000000); /* ymin, xmin */
184 *b++ = (DRAW_YMAX(HEIGHT - 1) |
185 DRAW_XMAX(WIDTH - 1));
186 /* yorig, xorig (relate to color buffer?) */
190 *b++ = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(1) | I1_LOAD_S(2) | I1_LOAD_S(6) | 2);
191 *b++ = ((4 << S1_VERTEX_WIDTH_SHIFT) | (4 << S1_VERTEX_PITCH_SHIFT));
192 *b++ = (~S2_TEXCOORD_FMT(0, TEXCOORDFMT_NOT_PRESENT) |
193 S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D));
194 *b++ = (S6_CBUF_BLEND_ENABLE | S6_COLOR_WRITE_ENABLE |
195 BLENDFUNC_ADD << S6_CBUF_BLEND_FUNC_SHIFT |
196 BLENDFACT_ONE << S6_CBUF_SRC_BLEND_FACT_SHIFT |
197 BLENDFACT_ZERO << S6_CBUF_DST_BLEND_FACT_SHIFT);
200 *b++ = (_3DSTATE_PIXEL_SHADER_PROGRAM | (1 + 3*3 - 2));
203 REG_TYPE(FS_T0) << D0_TYPE_SHIFT |
204 REG_NR(FS_T0) << D0_NR_SHIFT |
205 ((REG_TYPE(FS_T0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0));
210 (REG_TYPE(FS_S0) << D0_TYPE_SHIFT) |
211 (REG_NR(FS_S0) << D0_NR_SHIFT) |
212 ((REG_TYPE(FS_S0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0));
215 /* texld(FS_OC, FS_S0, FS_T0 */
217 (REG_TYPE(FS_OC) << T0_DEST_TYPE_SHIFT) |
218 (REG_NR(FS_OC) << T0_DEST_NR_SHIFT) |
219 (REG_NR(FS_S0) << T0_SAMPLER_NR_SHIFT));
220 *b++ = ((REG_TYPE(FS_T0) << T1_ADDRESS_REG_TYPE_SHIFT) |
221 (REG_NR(FS_T0) << T1_ADDRESS_REG_NR_SHIFT));
224 *b++ = (PRIM3D_RECTLIST | (3*4 - 1));
225 *b++ = pack_float(WIDTH);
226 *b++ = pack_float(HEIGHT);
227 *b++ = pack_float(WIDTH);
228 *b++ = pack_float(HEIGHT);
230 *b++ = pack_float(0);
231 *b++ = pack_float(HEIGHT);
232 *b++ = pack_float(0);
233 *b++ = pack_float(HEIGHT);
235 *b++ = pack_float(0);
236 *b++ = pack_float(0);
237 *b++ = pack_float(0);
238 *b++ = pack_float(0);
240 *b++ = MI_BATCH_BUFFER_END;
244 igt_assert(b - batch <= 1024);
245 handle = gem_create(fd, 4096);
246 gem_write(fd, handle, 0, batch, (b-batch)*sizeof(batch[0]));
248 igt_assert(r-reloc == 2);
251 obj[0].relocation_count = 0;
252 obj[0].relocs_ptr = 0;
253 obj[0].alignment = 0;
260 obj[1].relocation_count = 0;
261 obj[1].relocs_ptr = 0;
262 obj[1].alignment = 0;
268 obj[2].handle = handle;
269 obj[2].relocation_count = 2;
270 obj[2].relocs_ptr = (uintptr_t)reloc;
271 obj[2].alignment = 0;
274 obj[2].rsvd1 = obj[2].rsvd2 = 0;
276 exec.buffers_ptr = (uintptr_t)obj;
277 exec.buffer_count = 3;
278 exec.batch_start_offset = 0;
279 exec.batch_len = (b-batch)*sizeof(batch[0]);
280 exec.DR1 = exec.DR4 = 0;
281 exec.num_cliprects = 0;
282 exec.cliprects_ptr = 0;
284 i915_execbuffer2_set_context_id(exec, 0);
287 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
288 while (ret && errno == EBUSY) {
289 drmCommandNone(fd, DRM_I915_GEM_THROTTLE);
290 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
292 igt_assert(ret == 0);
294 gem_close(fd, handle);
298 create_bo(int fd, uint32_t val)
304 handle = gem_create(fd, WIDTH*HEIGHT*4);
305 gem_set_tiling(fd, handle, I915_TILING_Y, WIDTH*4);
307 /* Fill the BO with dwords starting at val */
308 v = gem_mmap(fd, handle, WIDTH*HEIGHT*4, PROT_READ | PROT_WRITE);
310 for (i = 0; i < WIDTH*HEIGHT; i++)
312 munmap(v, WIDTH*HEIGHT*4);
318 check_bo(int fd, uint32_t handle, uint32_t val)
323 v = gem_mmap(fd, handle, WIDTH*HEIGHT*4, PROT_READ);
325 for (i = 0; i < WIDTH*HEIGHT; i++) {
326 igt_assert_f(v[i] == val,
327 "Expected 0x%08x, found 0x%08x "
328 "at offset 0x%08x\n",
332 munmap(v, WIDTH*HEIGHT*4);
335 int main(int argc, char **argv)
337 uint32_t *handle, *start_val;
341 igt_simple_init(argc, argv);
345 igt_require(IS_GEN3(intel_get_drm_devid(fd)));
349 count = atoi(argv[1]);
351 count = 3 * gem_aperture_size(fd) / (1024*1024) / 2;
352 igt_info("Using %d 1MiB buffers\n", count);
354 handle = malloc(sizeof(uint32_t)*count*2);
355 start_val = handle + count;
357 for (i = 0; i < count; i++) {
358 handle[i] = create_bo(fd, start);
359 start_val[i] = start;
360 start += 1024 * 1024 / 4;
363 igt_info("Verifying initialisation..."); fflush(stdout);
364 for (i = 0; i < count; i++)
365 check_bo(fd, handle[i], start_val[i]);
368 igt_info("Cyclic blits, forward..."); fflush(stdout);
369 for (i = 0; i < count * 32; i++) {
371 int dst = (i + 1) % count;
373 copy(fd, handle[dst], handle[src]);
374 start_val[dst] = start_val[src];
376 igt_info("verifying..."); fflush(stdout);
377 for (i = 0; i < count; i++)
378 check_bo(fd, handle[i], start_val[i]);
381 igt_info("Cyclic blits, backward..."); fflush(stdout);
382 for (i = 0; i < count * 32; i++) {
383 int src = (i + 1) % count;
386 copy(fd, handle[dst], handle[src]);
387 start_val[dst] = start_val[src];
389 igt_info("verifying..."); fflush(stdout);
390 for (i = 0; i < count; i++)
391 check_bo(fd, handle[i], start_val[i]);
394 igt_info("Random blits..."); fflush(stdout);
395 for (i = 0; i < count * 32; i++) {
396 int src = random() % count;
397 int dst = random() % count;
400 dst = random() % count;
402 copy(fd, handle[dst], handle[src]);
403 start_val[dst] = start_val[src];
405 igt_info("verifying..."); fflush(stdout);
406 for (i = 0; i < count; i++)
407 check_bo(fd, handle[i], start_val[i]);