2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Chris Wilson <chris@chris-wilson.co.uk>
28 /** @file gen3_linear_render_blits.c
30 * This is a test of doing many blits, with a working set
31 * larger than the aperture size.
33 * The goal is to simply ensure the basics work.
44 #include <sys/ioctl.h>
46 #include "ioctl_wrappers.h"
49 #include "intel_chipset.h"
57 static inline uint32_t pack_float(float f)
67 static uint32_t fill_reloc(struct drm_i915_gem_relocation_entry *reloc,
71 uint32_t write_domain)
73 reloc->target_handle = handle;
75 reloc->offset = offset * sizeof(uint32_t);
76 reloc->presumed_offset = 0;
77 reloc->read_domains = read_domain;
78 reloc->write_domain = write_domain;
80 return reloc->presumed_offset + reloc->delta;
85 uint32_t dst, int dst_tiling,
86 uint32_t src, int src_tiling)
88 uint32_t batch[1024], *b = batch;
89 struct drm_i915_gem_relocation_entry reloc[2], *r = reloc;
90 struct drm_i915_gem_exec_object2 obj[3];
91 struct drm_i915_gem_execbuffer2 exec;
97 *b++ = (_3DSTATE_AA_CMD |
98 AA_LINE_ECAAR_WIDTH_ENABLE |
99 AA_LINE_ECAAR_WIDTH_1_0 |
100 AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
101 *b++ = (_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD |
103 IAB_MODIFY_FUNC | (BLENDFUNC_ADD << IAB_FUNC_SHIFT) |
104 IAB_MODIFY_SRC_FACTOR | (BLENDFACT_ONE <<
105 IAB_SRC_FACTOR_SHIFT) |
106 IAB_MODIFY_DST_FACTOR | (BLENDFACT_ZERO <<
107 IAB_DST_FACTOR_SHIFT));
108 *b++ = (_3DSTATE_DFLT_DIFFUSE_CMD);
110 *b++ = (_3DSTATE_DFLT_SPEC_CMD);
112 *b++ = (_3DSTATE_DFLT_Z_CMD);
114 *b++ = (_3DSTATE_COORD_SET_BINDINGS |
120 CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
121 *b++ = (_3DSTATE_RASTER_RULES_CMD |
122 ENABLE_POINT_RASTER_RULE |
123 OGL_POINT_RASTER_RULE |
124 ENABLE_LINE_STRIP_PROVOKE_VRTX |
125 ENABLE_TRI_FAN_PROVOKE_VRTX |
126 LINE_STRIP_PROVOKE_VRTX(1) |
127 TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D | TEXKILL_4D);
128 *b++ = (_3DSTATE_MODES_4_CMD |
129 ENABLE_LOGIC_OP_FUNC | LOGIC_OP_FUNC(LOGICOP_COPY) |
130 ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff) |
131 ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff));
132 *b++ = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | I1_LOAD_S(4) | I1_LOAD_S(5) | 2);
133 *b++ = (0x00000000); /* Disable texture coordinate wrap-shortest */
134 *b++ = ((1 << S4_POINT_WIDTH_SHIFT) |
138 *b++ = (0x00000000); /* Stencil. */
139 *b++ = (_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
140 *b++ = (_3DSTATE_SCISSOR_RECT_0_CMD);
143 *b++ = (_3DSTATE_DEPTH_SUBRECT_DISABLE);
144 *b++ = (_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
146 *b++ = (_3DSTATE_STIPPLE);
148 *b++ = (_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0);
152 if (src_tiling != I915_TILING_NONE)
153 tiling_bits = MS3_TILED_SURFACE;
154 if (src_tiling == I915_TILING_Y)
155 tiling_bits |= MS3_TILE_WALK;
158 *b++ = (_3DSTATE_MAP_STATE | (3 * TEX_COUNT));
159 *b++ = ((1 << TEX_COUNT) - 1);
160 *b = fill_reloc(r++, b-batch, src, I915_GEM_DOMAIN_SAMPLER, 0); b++;
161 *b++ = (MAPSURF_32BIT | MT_32BIT_ARGB8888 | tiling_bits |
162 (HEIGHT - 1) << MS3_HEIGHT_SHIFT |
163 (WIDTH - 1) << MS3_WIDTH_SHIFT);
164 *b++ = ((WIDTH-1) << MS4_PITCH_SHIFT);
166 *b++ = (_3DSTATE_SAMPLER_STATE | (3 * TEX_COUNT));
167 *b++ = ((1 << TEX_COUNT) - 1);
168 *b++ = (MIPFILTER_NONE << SS2_MIP_FILTER_SHIFT |
169 FILTER_NEAREST << SS2_MAG_FILTER_SHIFT |
170 FILTER_NEAREST << SS2_MIN_FILTER_SHIFT);
171 *b++ = (TEXCOORDMODE_WRAP << SS3_TCX_ADDR_MODE_SHIFT |
172 TEXCOORDMODE_WRAP << SS3_TCY_ADDR_MODE_SHIFT |
173 0 << SS3_TEXTUREMAP_INDEX_SHIFT);
176 /* render target state */
178 if (dst_tiling != I915_TILING_NONE)
179 tiling_bits = BUF_3D_TILED_SURFACE;
180 if (dst_tiling == I915_TILING_Y)
181 tiling_bits |= BUF_3D_TILE_WALK_Y;
182 *b++ = (_3DSTATE_BUF_INFO_CMD);
183 *b++ = (BUF_3D_ID_COLOR_BACK | tiling_bits | WIDTH*4);
184 *b = fill_reloc(r++, b-batch, dst,
185 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
188 *b++ = (_3DSTATE_DST_BUF_VARS_CMD);
189 *b++ = (COLR_BUF_ARGB8888 |
190 DSTORG_HORT_BIAS(0x8) |
191 DSTORG_VERT_BIAS(0x8));
193 /* draw rect is unconditional */
194 *b++ = (_3DSTATE_DRAW_RECT_CMD);
196 *b++ = (0x00000000); /* ymin, xmin */
197 *b++ = (DRAW_YMAX(HEIGHT - 1) |
198 DRAW_XMAX(WIDTH - 1));
199 /* yorig, xorig (relate to color buffer?) */
203 *b++ = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(1) | I1_LOAD_S(2) | I1_LOAD_S(6) | 2);
204 *b++ = ((4 << S1_VERTEX_WIDTH_SHIFT) | (4 << S1_VERTEX_PITCH_SHIFT));
205 *b++ = (~S2_TEXCOORD_FMT(0, TEXCOORDFMT_NOT_PRESENT) |
206 S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D));
207 *b++ = (S6_CBUF_BLEND_ENABLE | S6_COLOR_WRITE_ENABLE |
208 BLENDFUNC_ADD << S6_CBUF_BLEND_FUNC_SHIFT |
209 BLENDFACT_ONE << S6_CBUF_SRC_BLEND_FACT_SHIFT |
210 BLENDFACT_ZERO << S6_CBUF_DST_BLEND_FACT_SHIFT);
213 *b++ = (_3DSTATE_PIXEL_SHADER_PROGRAM | (1 + 3*3 - 2));
216 REG_TYPE(FS_T0) << D0_TYPE_SHIFT |
217 REG_NR(FS_T0) << D0_NR_SHIFT |
218 ((REG_TYPE(FS_T0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0));
223 (REG_TYPE(FS_S0) << D0_TYPE_SHIFT) |
224 (REG_NR(FS_S0) << D0_NR_SHIFT) |
225 ((REG_TYPE(FS_S0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0));
228 /* texld(FS_OC, FS_S0, FS_T0 */
230 (REG_TYPE(FS_OC) << T0_DEST_TYPE_SHIFT) |
231 (REG_NR(FS_OC) << T0_DEST_NR_SHIFT) |
232 (REG_NR(FS_S0) << T0_SAMPLER_NR_SHIFT));
233 *b++ = ((REG_TYPE(FS_T0) << T1_ADDRESS_REG_TYPE_SHIFT) |
234 (REG_NR(FS_T0) << T1_ADDRESS_REG_NR_SHIFT));
237 *b++ = (PRIM3D_RECTLIST | (3*4 - 1));
238 *b++ = pack_float(WIDTH);
239 *b++ = pack_float(HEIGHT);
240 *b++ = pack_float(WIDTH);
241 *b++ = pack_float(HEIGHT);
243 *b++ = pack_float(0);
244 *b++ = pack_float(HEIGHT);
245 *b++ = pack_float(0);
246 *b++ = pack_float(HEIGHT);
248 *b++ = pack_float(0);
249 *b++ = pack_float(0);
250 *b++ = pack_float(0);
251 *b++ = pack_float(0);
253 *b++ = MI_BATCH_BUFFER_END;
257 igt_assert(b - batch <= 1024);
258 handle = gem_create(fd, 4096);
259 gem_write(fd, handle, 0, batch, (b-batch)*sizeof(batch[0]));
261 igt_assert(r-reloc == 2);
264 obj[0].relocation_count = 0;
265 obj[0].relocs_ptr = 0;
266 obj[0].alignment = 0;
273 obj[1].relocation_count = 0;
274 obj[1].relocs_ptr = 0;
275 obj[1].alignment = 0;
281 obj[2].handle = handle;
282 obj[2].relocation_count = 2;
283 obj[2].relocs_ptr = (uintptr_t)reloc;
284 obj[2].alignment = 0;
287 obj[2].rsvd1 = obj[2].rsvd2 = 0;
289 exec.buffers_ptr = (uintptr_t)obj;
290 exec.buffer_count = 3;
291 exec.batch_start_offset = 0;
292 exec.batch_len = (b-batch)*sizeof(batch[0]);
293 exec.DR1 = exec.DR4 = 0;
294 exec.num_cliprects = 0;
295 exec.cliprects_ptr = 0;
297 i915_execbuffer2_set_context_id(exec, 0);
300 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
301 while (ret && errno == EBUSY) {
302 drmCommandNone(fd, DRM_I915_GEM_THROTTLE);
303 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
305 igt_assert(ret == 0);
307 gem_close(fd, handle);
311 create_bo(int fd, uint32_t val, int tiling)
317 handle = gem_create(fd, WIDTH*HEIGHT*4);
318 gem_set_tiling(fd, handle, tiling, WIDTH*4);
320 /* Fill the BO with dwords starting at val */
321 v = gem_mmap(fd, handle, WIDTH*HEIGHT*4, PROT_READ | PROT_WRITE);
323 for (i = 0; i < WIDTH*HEIGHT; i++)
325 munmap(v, WIDTH*HEIGHT*4);
331 check_bo(int fd, uint32_t handle, uint32_t val)
336 v = gem_mmap(fd, handle, WIDTH*HEIGHT*4, PROT_READ);
338 for (i = 0; i < WIDTH*HEIGHT; i++) {
339 igt_assert_f(v[i] == val,
340 "Expected 0x%08x, found 0x%08x "
341 "at offset 0x%08x\n",
345 munmap(v, WIDTH*HEIGHT*4);
348 int main(int argc, char **argv)
350 uint32_t *handle, *tiling, *start_val;
354 igt_simple_init(argc, argv);
358 igt_require(IS_GEN3(intel_get_drm_devid(fd)));
362 count = atoi(argv[1]);
364 count = 3 * gem_aperture_size(fd) / (1024*1024) / 2;
365 igt_info("Using %d 1MiB buffers\n", count);
367 handle = malloc(sizeof(uint32_t)*count*3);
368 tiling = handle + count;
369 start_val = tiling + count;
371 for (i = 0; i < count; i++) {
372 handle[i] = create_bo(fd, start, tiling[i] = i % 3);
373 start_val[i] = start;
374 start += 1024 * 1024 / 4;
377 igt_info("Verifying initialisation..."); fflush(stdout);
378 for (i = 0; i < count; i++)
379 check_bo(fd, handle[i], start_val[i]);
382 igt_info("Cyclic blits, forward..."); fflush(stdout);
383 for (i = 0; i < count * 32; i++) {
385 int dst = (i + 1) % count;
387 copy(fd, handle[dst], tiling[dst], handle[src], tiling[src]);
388 start_val[dst] = start_val[src];
390 igt_info("verifying..."); fflush(stdout);
391 for (i = 0; i < count; i++)
392 check_bo(fd, handle[i], start_val[i]);
395 igt_info("Cyclic blits, backward..."); fflush(stdout);
396 for (i = 0; i < count * 32; i++) {
397 int src = (i + 1) % count;
400 copy(fd, handle[dst], tiling[dst], handle[src], tiling[src]);
401 start_val[dst] = start_val[src];
403 igt_info("verifying..."); fflush(stdout);
404 for (i = 0; i < count; i++)
405 check_bo(fd, handle[i], start_val[i]);
408 igt_info("Random blits..."); fflush(stdout);
409 for (i = 0; i < count * 32; i++) {
410 int src = random() % count;
411 int dst = random() % count;
414 dst = random() % count;
416 copy(fd, handle[dst], tiling[dst], handle[src], tiling[src]);
417 start_val[dst] = start_val[src];
419 igt_info("verifying..."); fflush(stdout);
420 for (i = 0; i < count; i++)
421 check_bo(fd, handle[i], start_val[i]);