2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Chris Wilson <chris@chris-wilson.co.uk>
28 /** @file gen3_linear_render_blits.c
30 * This is a test of doing many blits, with a working set
31 * larger than the aperture size.
33 * The goal is to simply ensure the basics work.
46 #include <sys/ioctl.h>
50 #include "intel_gpu_tools.h"
58 static inline uint32_t pack_float(float f)
68 static uint32_t gem_create(int fd, int size)
70 struct drm_i915_gem_create create;
74 (void)drmIoctl(fd, DRM_IOCTL_I915_GEM_CREATE, &create);
75 assert(create.handle);
80 static void gem_close(int fd, uint32_t handle)
82 struct drm_gem_close close;
85 close.handle = handle;
86 ret = drmIoctl(fd, DRM_IOCTL_GEM_CLOSE, &close);
91 gem_aperture_size(int fd)
93 struct drm_i915_gem_get_aperture aperture;
95 aperture.aper_size = 512*1024*1024;
96 (void)drmIoctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
97 return aperture.aper_size;
101 gem_write(int fd, uint32_t handle, int offset, int size, const void *buf)
103 struct drm_i915_gem_pwrite pwrite;
106 pwrite.handle = handle;
107 pwrite.offset = offset;
109 pwrite.data_ptr = (uintptr_t)buf;
110 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_PWRITE, &pwrite);
114 static uint32_t fill_reloc(struct drm_i915_gem_relocation_entry *reloc,
117 uint32_t read_domain,
118 uint32_t write_domain)
120 reloc->target_handle = handle;
122 reloc->offset = offset * sizeof(uint32_t);
123 reloc->presumed_offset = 0;
124 reloc->read_domains = read_domain;
125 reloc->write_domain = write_domain;
127 return reloc->presumed_offset + reloc->delta;
132 uint32_t dst, int dst_tiling,
133 uint32_t src, int src_tiling)
135 uint32_t batch[1024], *b = batch;
136 struct drm_i915_gem_relocation_entry reloc[2], *r = reloc;
137 struct drm_i915_gem_exec_object2 obj[3];
138 struct drm_i915_gem_execbuffer2 exec;
140 uint32_t tiling_bits;
143 /* invariant state */
144 *b++ = (_3DSTATE_AA_CMD |
145 AA_LINE_ECAAR_WIDTH_ENABLE |
146 AA_LINE_ECAAR_WIDTH_1_0 |
147 AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
148 *b++ = (_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD |
150 IAB_MODIFY_FUNC | (BLENDFUNC_ADD << IAB_FUNC_SHIFT) |
151 IAB_MODIFY_SRC_FACTOR |
152 (BLENDFACT_ONE << IAB_SRC_FACTOR_SHIFT) |
153 IAB_MODIFY_DST_FACTOR |
154 (BLENDFACT_ZERO << IAB_DST_FACTOR_SHIFT));
155 *b++ = (_3DSTATE_DFLT_DIFFUSE_CMD);
157 *b++ = (_3DSTATE_DFLT_SPEC_CMD);
159 *b++ = (_3DSTATE_DFLT_Z_CMD);
161 *b++ = (_3DSTATE_COORD_SET_BINDINGS |
170 *b++ = (_3DSTATE_RASTER_RULES_CMD |
171 ENABLE_POINT_RASTER_RULE |
172 OGL_POINT_RASTER_RULE |
173 ENABLE_LINE_STRIP_PROVOKE_VRTX |
174 ENABLE_TRI_FAN_PROVOKE_VRTX |
175 LINE_STRIP_PROVOKE_VRTX(1) |
176 TRI_FAN_PROVOKE_VRTX(2) |
177 ENABLE_TEXKILL_3D_4D |
179 *b++ = (_3DSTATE_MODES_4_CMD |
180 ENABLE_LOGIC_OP_FUNC | LOGIC_OP_FUNC(LOGICOP_COPY) |
181 ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff) |
182 ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff));
183 *b++ = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | I1_LOAD_S(4) | I1_LOAD_S(5) | 2);
184 *b++ = (0x00000000); /* Disable texture coordinate wrap-shortest */
185 *b++ = ((1 << S4_POINT_WIDTH_SHIFT) |
189 *b++ = (0x00000000); /* Stencil. */
190 *b++ = (_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
191 *b++ = (_3DSTATE_SCISSOR_RECT_0_CMD);
194 *b++ = (_3DSTATE_DEPTH_SUBRECT_DISABLE);
195 *b++ = (_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
197 *b++ = (_3DSTATE_STIPPLE);
199 *b++ = (_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0);
203 if (src_tiling != I915_TILING_NONE)
204 tiling_bits = MS3_TILED_SURFACE;
205 if (src_tiling == I915_TILING_Y)
206 tiling_bits |= MS3_TILE_WALK;
209 *b++ = (_3DSTATE_MAP_STATE | (3 * TEX_COUNT));
210 *b++ = ((1 << TEX_COUNT) - 1);
211 *b = fill_reloc(r++, b-batch, src, I915_GEM_DOMAIN_SAMPLER, 0); b++;
212 *b++ = (MAPSURF_32BIT | MT_32BIT_ARGB8888 | tiling_bits |
213 (HEIGHT - 1) << MS3_HEIGHT_SHIFT |
214 (WIDTH - 1) << MS3_WIDTH_SHIFT);
215 *b++ = ((WIDTH-1) << MS4_PITCH_SHIFT);
217 *b++ = (_3DSTATE_SAMPLER_STATE | (3 * TEX_COUNT));
218 *b++ = ((1 << TEX_COUNT) - 1);
219 *b++ = (MIPFILTER_NONE << SS2_MIP_FILTER_SHIFT |
220 FILTER_NEAREST << SS2_MAG_FILTER_SHIFT |
221 FILTER_NEAREST << SS2_MIN_FILTER_SHIFT);
222 *b++ = (TEXCOORDMODE_WRAP << SS3_TCX_ADDR_MODE_SHIFT |
223 TEXCOORDMODE_WRAP << SS3_TCY_ADDR_MODE_SHIFT |
224 0 << SS3_TEXTUREMAP_INDEX_SHIFT);
227 /* render target state */
229 if (dst_tiling != I915_TILING_NONE)
230 tiling_bits = BUF_3D_TILED_SURFACE;
231 if (dst_tiling == I915_TILING_Y)
232 tiling_bits |= BUF_3D_TILE_WALK_Y;
233 *b++ = (_3DSTATE_BUF_INFO_CMD);
234 *b++ = (BUF_3D_ID_COLOR_BACK | tiling_bits | WIDTH*4);
235 *b = fill_reloc(r++, b-batch, dst,
236 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
239 *b++ = (_3DSTATE_DST_BUF_VARS_CMD);
240 *b++ = (COLR_BUF_ARGB8888 |
241 DSTORG_HORT_BIAS(0x8) |
242 DSTORG_VERT_BIAS(0x8));
244 /* draw rect is unconditional */
245 *b++ = (_3DSTATE_DRAW_RECT_CMD);
247 *b++ = (0x00000000); /* ymin, xmin */
248 *b++ = (DRAW_YMAX(HEIGHT - 1) |
249 DRAW_XMAX(WIDTH - 1));
250 /* yorig, xorig (relate to color buffer?) */
254 *b++ = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(1) | I1_LOAD_S(2) | I1_LOAD_S(6) | 2);
255 *b++ = ((4 << S1_VERTEX_WIDTH_SHIFT) | (4 << S1_VERTEX_PITCH_SHIFT));
256 *b++ = (~S2_TEXCOORD_FMT(0, TEXCOORDFMT_NOT_PRESENT) |
257 S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D));
258 *b++ = (S6_CBUF_BLEND_ENABLE | S6_COLOR_WRITE_ENABLE |
259 BLENDFUNC_ADD << S6_CBUF_BLEND_FUNC_SHIFT |
260 BLENDFACT_ONE << S6_CBUF_SRC_BLEND_FACT_SHIFT |
261 BLENDFACT_ZERO << S6_CBUF_DST_BLEND_FACT_SHIFT);
264 *b++ = (_3DSTATE_PIXEL_SHADER_PROGRAM | (1 + 3*3 - 2));
267 REG_TYPE(FS_T0) << D0_TYPE_SHIFT |
268 REG_NR(FS_T0) << D0_NR_SHIFT |
269 ((REG_TYPE(FS_T0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0));
274 (REG_TYPE(FS_S0) << D0_TYPE_SHIFT) |
275 (REG_NR(FS_S0) << D0_NR_SHIFT) |
276 ((REG_TYPE(FS_S0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0));
279 /* texld(FS_OC, FS_S0, FS_T0 */
281 (REG_TYPE(FS_OC) << T0_DEST_TYPE_SHIFT) |
282 (REG_NR(FS_OC) << T0_DEST_NR_SHIFT) |
283 (REG_NR(FS_S0) << T0_SAMPLER_NR_SHIFT));
284 *b++ = ((REG_TYPE(FS_T0) << T1_ADDRESS_REG_TYPE_SHIFT) |
285 (REG_NR(FS_T0) << T1_ADDRESS_REG_NR_SHIFT));
288 *b++ = (PRIM3D_RECTLIST | (3*4 - 1));
289 *b++ = pack_float(WIDTH);
290 *b++ = pack_float(HEIGHT);
291 *b++ = pack_float(WIDTH);
292 *b++ = pack_float(HEIGHT);
294 *b++ = pack_float(0);
295 *b++ = pack_float(HEIGHT);
296 *b++ = pack_float(0);
297 *b++ = pack_float(HEIGHT);
299 *b++ = pack_float(0);
300 *b++ = pack_float(0);
301 *b++ = pack_float(0);
302 *b++ = pack_float(0);
304 *b++ = MI_BATCH_BUFFER_END;
308 assert(b - batch <= 1024);
309 handle = gem_create(fd, 4096);
310 gem_write(fd, handle, 0, (b-batch)*sizeof(batch[0]), batch);
312 assert(r-reloc == 2);
315 obj[0].relocation_count = 0;
316 obj[0].relocs_ptr = 0;
317 obj[0].alignment = 0;
324 obj[1].relocation_count = 0;
325 obj[1].relocs_ptr = 0;
326 obj[1].alignment = 0;
332 obj[2].handle = handle;
333 obj[2].relocation_count = 2;
334 obj[2].relocs_ptr = (uintptr_t)reloc;
335 obj[2].alignment = 0;
338 obj[2].rsvd1 = obj[2].rsvd2 = 0;
340 exec.buffers_ptr = (uintptr_t)obj;
341 exec.buffer_count = 3;
342 exec.batch_start_offset = 0;
343 exec.batch_len = (b-batch)*sizeof(batch[0]);
344 exec.DR1 = exec.DR4 = 0;
345 exec.num_cliprects = 0;
346 exec.cliprects_ptr = 0;
348 exec.rsvd1 = exec.rsvd2 = 0;
350 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
351 while (ret && errno == EBUSY) {
352 drmCommandNone(fd, DRM_I915_GEM_THROTTLE);
353 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
357 gem_close(fd, handle);
360 static void blt_copy(int fd, uint32_t dst, uint32_t src)
362 uint32_t batch[1024], *b = batch;
363 struct drm_i915_gem_relocation_entry reloc[2], *r = reloc;
364 struct drm_i915_gem_exec_object2 obj[3];
365 struct drm_i915_gem_execbuffer2 exec;
369 *b++ = (XY_SRC_COPY_BLT_CMD |
370 XY_SRC_COPY_BLT_WRITE_ALPHA |
371 XY_SRC_COPY_BLT_WRITE_RGB);
372 *b++ = 3 << 24 | 0xcc << 16 | WIDTH * 4;
374 *b++ = HEIGHT << 16 | WIDTH;
375 *b = fill_reloc(r++, b-batch, dst,
376 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER); b++;
379 *b = fill_reloc(r++, b-batch, src, I915_GEM_DOMAIN_RENDER, 0); b++;
381 *b++ = MI_BATCH_BUFFER_END;
385 assert(b - batch <= 1024);
386 handle = gem_create(fd, 4096);
387 gem_write(fd, handle, 0, (b-batch)*sizeof(batch[0]), batch);
389 assert(r-reloc == 2);
392 obj[0].relocation_count = 0;
393 obj[0].relocs_ptr = 0;
394 obj[0].alignment = 0;
396 obj[0].flags = EXEC_OBJECT_NEEDS_FENCE;
401 obj[1].relocation_count = 0;
402 obj[1].relocs_ptr = 0;
403 obj[1].alignment = 0;
405 obj[1].flags = EXEC_OBJECT_NEEDS_FENCE;
409 obj[2].handle = handle;
410 obj[2].relocation_count = 2;
411 obj[2].relocs_ptr = (uintptr_t)reloc;
412 obj[2].alignment = 0;
415 obj[2].rsvd1 = obj[2].rsvd2 = 0;
417 exec.buffers_ptr = (uintptr_t)obj;
418 exec.buffer_count = 3;
419 exec.batch_start_offset = 0;
420 exec.batch_len = (b-batch)*sizeof(batch[0]);
421 exec.DR1 = exec.DR4 = 0;
422 exec.num_cliprects = 0;
423 exec.cliprects_ptr = 0;
425 exec.rsvd1 = exec.rsvd2 = 0;
427 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
428 while (ret && errno == EBUSY) {
429 drmCommandNone(fd, DRM_I915_GEM_THROTTLE);
430 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
434 gem_close(fd, handle);
437 static void *gem_mmap(int fd, uint32_t handle, int size, int prot)
439 struct drm_i915_gem_mmap_gtt mmap_arg;
442 mmap_arg.handle = handle;
443 if (drmIoctl(fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &mmap_arg)) {
448 ptr = mmap(0, size, prot, MAP_SHARED, fd, mmap_arg.offset);
449 if (ptr == MAP_FAILED) {
457 static void gem_set_tiling(int fd, uint32_t handle, int tiling, int stride)
459 struct drm_i915_gem_set_tiling set_tiling;
463 set_tiling.handle = handle;
464 set_tiling.tiling_mode = tiling;
465 set_tiling.stride = stride;
467 ret = ioctl(fd, DRM_IOCTL_I915_GEM_SET_TILING, &set_tiling);
468 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
470 assert(set_tiling.tiling_mode == tiling);
474 create_bo(int fd, uint32_t val, int tiling)
480 handle = gem_create(fd, WIDTH*HEIGHT*4);
481 gem_set_tiling(fd, handle, tiling, WIDTH*4);
483 /* Fill the BO with dwords starting at val */
484 v = gem_mmap(fd, handle, WIDTH*HEIGHT*4, PROT_READ | PROT_WRITE);
485 for (i = 0; i < WIDTH*HEIGHT; i++)
487 munmap(v, WIDTH*HEIGHT*4);
493 check_bo(int fd, uint32_t handle, uint32_t val)
498 v = gem_mmap(fd, handle, WIDTH*HEIGHT*4, PROT_READ);
499 for (i = 0; i < WIDTH*HEIGHT; i++) {
501 fprintf(stderr, "Expected 0x%08x, found 0x%08x "
502 "at offset 0x%08x\n",
508 munmap(v, WIDTH*HEIGHT*4);
511 int main(int argc, char **argv)
513 uint32_t *handle, *tiling, *start_val;
521 count = atoi(argv[1]);
523 count = 3 * gem_aperture_size(fd) / (1024*1024) / 2;
524 printf("Using %d 1MiB buffers\n", count);
526 handle = malloc(sizeof(uint32_t)*count*3);
527 tiling = handle + count;
528 start_val = tiling + count;
530 for (i = 0; i < count; i++) {
531 handle[i] = create_bo(fd, start, tiling[i] = i % 3);
532 start_val[i] = start;
533 start += 1024 * 1024 / 4;
536 printf("Verifying initialisation..."); fflush(stdout);
537 for (i = 0; i < count; i++)
538 check_bo(fd, handle[i], start_val[i]);
541 printf("Cyclic blits, forward..."); fflush(stdout);
542 for (i = 0; i < count * 32; i++) {
544 int dst = (i + 1) % count;
547 render_copy(fd, handle[dst], tiling[dst], handle[src], tiling[src]);
549 blt_copy(fd, handle[dst], handle[src]);
550 start_val[dst] = start_val[src];
552 printf("verifying..."); fflush(stdout);
553 for (i = 0; i < count; i++)
554 check_bo(fd, handle[i], start_val[i]);
557 printf("Cyclic blits, backward..."); fflush(stdout);
558 for (i = 0; i < count * 32; i++) {
559 int src = (i + 1) % count;
563 render_copy(fd, handle[dst], tiling[dst], handle[src], tiling[src]);
565 blt_copy(fd, handle[dst], handle[src]);
566 start_val[dst] = start_val[src];
568 printf("verifying..."); fflush(stdout);
569 for (i = 0; i < count; i++)
570 check_bo(fd, handle[i], start_val[i]);
573 printf("Random blits..."); fflush(stdout);
574 for (i = 0; i < count * 32; i++) {
575 int src = random() % count;
576 int dst = random() % count;
579 dst = random() % count;
582 render_copy(fd, handle[dst], tiling[dst], handle[src], tiling[src]);
584 blt_copy(fd, handle[dst], handle[src]);
585 start_val[dst] = start_val[src];
587 printf("verifying..."); fflush(stdout);
588 for (i = 0; i < count; i++)
589 check_bo(fd, handle[i], start_val[i]);