2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Chris Wilson <chris@chris-wilson.co.uk>
28 /** @file gen3_linear_render_blits.c
30 * This is a test of doing many blits, with a working set
31 * larger than the aperture size.
33 * The goal is to simply ensure the basics work.
46 #include <sys/ioctl.h>
50 #include "intel_gpu_tools.h"
58 static inline uint32_t pack_float(float f)
68 static uint32_t gem_create(int fd, int size)
70 struct drm_i915_gem_create create;
74 (void)drmIoctl(fd, DRM_IOCTL_I915_GEM_CREATE, &create);
75 assert(create.handle);
80 static void gem_close(int fd, uint32_t handle)
82 struct drm_gem_close close;
85 close.handle = handle;
86 ret = drmIoctl(fd, DRM_IOCTL_GEM_CLOSE, &close);
91 gem_aperture_size(int fd)
93 struct drm_i915_gem_get_aperture aperture;
95 aperture.aper_size = 512*1024*1024;
96 (void)drmIoctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
97 return aperture.aper_size;
101 gem_write(int fd, uint32_t handle, int offset, int size, const void *buf)
103 struct drm_i915_gem_pwrite pwrite;
106 pwrite.handle = handle;
107 pwrite.offset = offset;
109 pwrite.data_ptr = (uintptr_t)buf;
110 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_PWRITE, &pwrite);
114 static uint32_t fill_reloc(struct drm_i915_gem_relocation_entry *reloc,
117 uint32_t read_domain,
118 uint32_t write_domain)
120 reloc->target_handle = handle;
122 reloc->offset = offset * sizeof(uint32_t);
123 reloc->presumed_offset = 0;
124 reloc->read_domains = read_domain;
125 reloc->write_domain = write_domain;
127 return reloc->presumed_offset + reloc->delta;
132 uint32_t dst, int dst_tiling,
133 uint32_t src, int src_tiling,
136 uint32_t batch[1024], *b = batch;
137 struct drm_i915_gem_relocation_entry reloc[2], *r = reloc;
138 struct drm_i915_gem_exec_object2 obj[3];
139 struct drm_i915_gem_execbuffer2 exec;
141 uint32_t tiling_bits;
144 /* invariant state */
145 *b++ = (_3DSTATE_AA_CMD |
146 AA_LINE_ECAAR_WIDTH_ENABLE |
147 AA_LINE_ECAAR_WIDTH_1_0 |
148 AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
149 *b++ = (_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD |
151 IAB_MODIFY_FUNC | (BLENDFUNC_ADD << IAB_FUNC_SHIFT) |
152 IAB_MODIFY_SRC_FACTOR |
153 (BLENDFACT_ONE << IAB_SRC_FACTOR_SHIFT) |
154 IAB_MODIFY_DST_FACTOR |
155 (BLENDFACT_ZERO << IAB_DST_FACTOR_SHIFT));
156 *b++ = (_3DSTATE_DFLT_DIFFUSE_CMD);
158 *b++ = (_3DSTATE_DFLT_SPEC_CMD);
160 *b++ = (_3DSTATE_DFLT_Z_CMD);
162 *b++ = (_3DSTATE_COORD_SET_BINDINGS |
171 *b++ = (_3DSTATE_RASTER_RULES_CMD |
172 ENABLE_POINT_RASTER_RULE |
173 OGL_POINT_RASTER_RULE |
174 ENABLE_LINE_STRIP_PROVOKE_VRTX |
175 ENABLE_TRI_FAN_PROVOKE_VRTX |
176 LINE_STRIP_PROVOKE_VRTX(1) |
177 TRI_FAN_PROVOKE_VRTX(2) |
178 ENABLE_TEXKILL_3D_4D |
180 *b++ = (_3DSTATE_MODES_4_CMD |
181 ENABLE_LOGIC_OP_FUNC | LOGIC_OP_FUNC(LOGICOP_COPY) |
182 ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff) |
183 ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff));
184 *b++ = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | I1_LOAD_S(4) | I1_LOAD_S(5) | 2);
185 *b++ = (0x00000000); /* Disable texture coordinate wrap-shortest */
186 *b++ = ((1 << S4_POINT_WIDTH_SHIFT) |
190 *b++ = (0x00000000); /* Stencil. */
191 *b++ = (_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
192 *b++ = (_3DSTATE_SCISSOR_RECT_0_CMD);
195 *b++ = (_3DSTATE_DEPTH_SUBRECT_DISABLE);
196 *b++ = (_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
198 *b++ = (_3DSTATE_STIPPLE);
200 *b++ = (_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0);
204 tiling_bits = MS3_USE_FENCE_REGS;
207 if (src_tiling != I915_TILING_NONE)
208 tiling_bits = MS3_TILED_SURFACE;
209 if (src_tiling == I915_TILING_Y)
210 tiling_bits |= MS3_TILE_WALK;
214 *b++ = (_3DSTATE_MAP_STATE | (3 * TEX_COUNT));
215 *b++ = ((1 << TEX_COUNT) - 1);
216 *b = fill_reloc(r++, b-batch, src, I915_GEM_DOMAIN_SAMPLER, 0); b++;
217 *b++ = (MAPSURF_32BIT | MT_32BIT_ARGB8888 | tiling_bits |
218 (HEIGHT - 1) << MS3_HEIGHT_SHIFT |
219 (WIDTH - 1) << MS3_WIDTH_SHIFT);
220 *b++ = ((WIDTH-1) << MS4_PITCH_SHIFT);
222 *b++ = (_3DSTATE_SAMPLER_STATE | (3 * TEX_COUNT));
223 *b++ = ((1 << TEX_COUNT) - 1);
224 *b++ = (MIPFILTER_NONE << SS2_MIP_FILTER_SHIFT |
225 FILTER_NEAREST << SS2_MAG_FILTER_SHIFT |
226 FILTER_NEAREST << SS2_MIN_FILTER_SHIFT);
227 *b++ = (TEXCOORDMODE_WRAP << SS3_TCX_ADDR_MODE_SHIFT |
228 TEXCOORDMODE_WRAP << SS3_TCY_ADDR_MODE_SHIFT |
229 0 << SS3_TEXTUREMAP_INDEX_SHIFT);
232 /* render target state */
234 tiling_bits = BUF_3D_USE_FENCE;
237 if (dst_tiling != I915_TILING_NONE)
238 tiling_bits = BUF_3D_TILED_SURFACE;
239 if (dst_tiling == I915_TILING_Y)
240 tiling_bits |= BUF_3D_TILE_WALK_Y;
242 *b++ = (_3DSTATE_BUF_INFO_CMD);
243 *b++ = (BUF_3D_ID_COLOR_BACK | tiling_bits | WIDTH*4);
244 *b = fill_reloc(r++, b-batch, dst,
245 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
248 *b++ = (_3DSTATE_DST_BUF_VARS_CMD);
249 *b++ = (COLR_BUF_ARGB8888 |
250 DSTORG_HORT_BIAS(0x8) |
251 DSTORG_VERT_BIAS(0x8));
253 /* draw rect is unconditional */
254 *b++ = (_3DSTATE_DRAW_RECT_CMD);
256 *b++ = (0x00000000); /* ymin, xmin */
257 *b++ = (DRAW_YMAX(HEIGHT - 1) |
258 DRAW_XMAX(WIDTH - 1));
259 /* yorig, xorig (relate to color buffer?) */
263 *b++ = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(1) | I1_LOAD_S(2) | I1_LOAD_S(6) | 2);
264 *b++ = ((4 << S1_VERTEX_WIDTH_SHIFT) | (4 << S1_VERTEX_PITCH_SHIFT));
265 *b++ = (~S2_TEXCOORD_FMT(0, TEXCOORDFMT_NOT_PRESENT) |
266 S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D));
267 *b++ = (S6_CBUF_BLEND_ENABLE | S6_COLOR_WRITE_ENABLE |
268 BLENDFUNC_ADD << S6_CBUF_BLEND_FUNC_SHIFT |
269 BLENDFACT_ONE << S6_CBUF_SRC_BLEND_FACT_SHIFT |
270 BLENDFACT_ZERO << S6_CBUF_DST_BLEND_FACT_SHIFT);
273 *b++ = (_3DSTATE_PIXEL_SHADER_PROGRAM | (1 + 3*3 - 2));
276 REG_TYPE(FS_T0) << D0_TYPE_SHIFT |
277 REG_NR(FS_T0) << D0_NR_SHIFT |
278 ((REG_TYPE(FS_T0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0));
283 (REG_TYPE(FS_S0) << D0_TYPE_SHIFT) |
284 (REG_NR(FS_S0) << D0_NR_SHIFT) |
285 ((REG_TYPE(FS_S0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0));
288 /* texld(FS_OC, FS_S0, FS_T0 */
290 (REG_TYPE(FS_OC) << T0_DEST_TYPE_SHIFT) |
291 (REG_NR(FS_OC) << T0_DEST_NR_SHIFT) |
292 (REG_NR(FS_S0) << T0_SAMPLER_NR_SHIFT));
293 *b++ = ((REG_TYPE(FS_T0) << T1_ADDRESS_REG_TYPE_SHIFT) |
294 (REG_NR(FS_T0) << T1_ADDRESS_REG_NR_SHIFT));
297 *b++ = (PRIM3D_RECTLIST | (3*4 - 1));
298 *b++ = pack_float(WIDTH);
299 *b++ = pack_float(HEIGHT);
300 *b++ = pack_float(WIDTH);
301 *b++ = pack_float(HEIGHT);
303 *b++ = pack_float(0);
304 *b++ = pack_float(HEIGHT);
305 *b++ = pack_float(0);
306 *b++ = pack_float(HEIGHT);
308 *b++ = pack_float(0);
309 *b++ = pack_float(0);
310 *b++ = pack_float(0);
311 *b++ = pack_float(0);
313 *b++ = MI_BATCH_BUFFER_END;
317 assert(b - batch <= 1024);
318 handle = gem_create(fd, 4096);
319 gem_write(fd, handle, 0, (b-batch)*sizeof(batch[0]), batch);
321 assert(r-reloc == 2);
325 tiling_bits = EXEC_OBJECT_NEEDS_FENCE;
328 obj[0].relocation_count = 0;
329 obj[0].relocs_ptr = 0;
330 obj[0].alignment = 0;
332 obj[0].flags = tiling_bits;
337 obj[1].relocation_count = 0;
338 obj[1].relocs_ptr = 0;
339 obj[1].alignment = 0;
341 obj[1].flags = tiling_bits;
345 obj[2].handle = handle;
346 obj[2].relocation_count = 2;
347 obj[2].relocs_ptr = (uintptr_t)reloc;
348 obj[2].alignment = 0;
351 obj[2].rsvd1 = obj[2].rsvd2 = 0;
353 exec.buffers_ptr = (uintptr_t)obj;
354 exec.buffer_count = 3;
355 exec.batch_start_offset = 0;
356 exec.batch_len = (b-batch)*sizeof(batch[0]);
357 exec.DR1 = exec.DR4 = 0;
358 exec.num_cliprects = 0;
359 exec.cliprects_ptr = 0;
361 exec.rsvd1 = exec.rsvd2 = 0;
363 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
364 while (ret && errno == EBUSY) {
365 drmCommandNone(fd, DRM_I915_GEM_THROTTLE);
366 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
370 gem_close(fd, handle);
373 static void blt_copy(int fd, uint32_t dst, uint32_t src)
375 uint32_t batch[1024], *b = batch;
376 struct drm_i915_gem_relocation_entry reloc[2], *r = reloc;
377 struct drm_i915_gem_exec_object2 obj[3];
378 struct drm_i915_gem_execbuffer2 exec;
382 *b++ = (XY_SRC_COPY_BLT_CMD |
383 XY_SRC_COPY_BLT_WRITE_ALPHA |
384 XY_SRC_COPY_BLT_WRITE_RGB);
385 *b++ = 3 << 24 | 0xcc << 16 | WIDTH * 4;
387 *b++ = HEIGHT << 16 | WIDTH;
388 *b = fill_reloc(r++, b-batch, dst,
389 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER); b++;
392 *b = fill_reloc(r++, b-batch, src, I915_GEM_DOMAIN_RENDER, 0); b++;
394 *b++ = MI_BATCH_BUFFER_END;
398 assert(b - batch <= 1024);
399 handle = gem_create(fd, 4096);
400 gem_write(fd, handle, 0, (b-batch)*sizeof(batch[0]), batch);
402 assert(r-reloc == 2);
405 obj[0].relocation_count = 0;
406 obj[0].relocs_ptr = 0;
407 obj[0].alignment = 0;
409 obj[0].flags = EXEC_OBJECT_NEEDS_FENCE;
414 obj[1].relocation_count = 0;
415 obj[1].relocs_ptr = 0;
416 obj[1].alignment = 0;
418 obj[1].flags = EXEC_OBJECT_NEEDS_FENCE;
422 obj[2].handle = handle;
423 obj[2].relocation_count = 2;
424 obj[2].relocs_ptr = (uintptr_t)reloc;
425 obj[2].alignment = 0;
428 obj[2].rsvd1 = obj[2].rsvd2 = 0;
430 exec.buffers_ptr = (uintptr_t)obj;
431 exec.buffer_count = 3;
432 exec.batch_start_offset = 0;
433 exec.batch_len = (b-batch)*sizeof(batch[0]);
434 exec.DR1 = exec.DR4 = 0;
435 exec.num_cliprects = 0;
436 exec.cliprects_ptr = 0;
438 exec.rsvd1 = exec.rsvd2 = 0;
440 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
441 while (ret && errno == EBUSY) {
442 drmCommandNone(fd, DRM_I915_GEM_THROTTLE);
443 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
447 gem_close(fd, handle);
453 uint32_t dst, int dst_tiling,
454 uint32_t src, int src_tiling)
456 switch (random() % 3) {
457 case 0: render_copy(fd, dst, dst_tiling, src, src_tiling, 0); break;
458 case 1: render_copy(fd, dst, dst_tiling, src, src_tiling, 1); break;
459 case 2: blt_copy(fd, dst, src); break;
463 static void *gem_mmap(int fd, uint32_t handle, int size, int prot)
465 struct drm_i915_gem_mmap_gtt mmap_arg;
468 mmap_arg.handle = handle;
469 if (drmIoctl(fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &mmap_arg)) {
474 ptr = mmap(0, size, prot, MAP_SHARED, fd, mmap_arg.offset);
475 if (ptr == MAP_FAILED) {
483 static void gem_set_tiling(int fd, uint32_t handle, int tiling, int stride)
485 struct drm_i915_gem_set_tiling set_tiling;
489 set_tiling.handle = handle;
490 set_tiling.tiling_mode = tiling;
491 set_tiling.stride = stride;
493 ret = ioctl(fd, DRM_IOCTL_I915_GEM_SET_TILING, &set_tiling);
494 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
496 assert(set_tiling.tiling_mode == tiling);
500 create_bo(int fd, uint32_t val, int tiling)
506 handle = gem_create(fd, WIDTH*HEIGHT*4);
507 gem_set_tiling(fd, handle, tiling, WIDTH*4);
509 /* Fill the BO with dwords starting at val */
510 v = gem_mmap(fd, handle, WIDTH*HEIGHT*4, PROT_READ | PROT_WRITE);
511 for (i = 0; i < WIDTH*HEIGHT; i++)
513 munmap(v, WIDTH*HEIGHT*4);
519 check_bo(int fd, uint32_t handle, uint32_t val)
524 v = gem_mmap(fd, handle, WIDTH*HEIGHT*4, PROT_READ);
525 for (i = 0; i < WIDTH*HEIGHT; i++) {
527 fprintf(stderr, "Expected 0x%08x, found 0x%08x "
528 "at offset 0x%08x\n",
534 munmap(v, WIDTH*HEIGHT*4);
537 int main(int argc, char **argv)
539 uint32_t *handle, *tiling, *start_val;
547 count = atoi(argv[1]);
549 count = 3 * gem_aperture_size(fd) / (1024*1024) / 2;
550 printf("Using %d 1MiB buffers\n", count);
552 handle = malloc(sizeof(uint32_t)*count*3);
553 tiling = handle + count;
554 start_val = tiling + count;
556 for (i = 0; i < count; i++) {
557 handle[i] = create_bo(fd, start, tiling[i] = i % 3);
558 start_val[i] = start;
559 start += 1024 * 1024 / 4;
562 printf("Verifying initialisation..."); fflush(stdout);
563 for (i = 0; i < count; i++)
564 check_bo(fd, handle[i], start_val[i]);
567 printf("Cyclic blits, forward..."); fflush(stdout);
568 for (i = 0; i < count * 32; i++) {
570 int dst = (i + 1) % count;
572 copy(fd, handle[dst], tiling[dst], handle[src], tiling[src]);
573 start_val[dst] = start_val[src];
575 printf("verifying..."); fflush(stdout);
576 for (i = 0; i < count; i++)
577 check_bo(fd, handle[i], start_val[i]);
580 printf("Cyclic blits, backward..."); fflush(stdout);
581 for (i = 0; i < count * 32; i++) {
582 int src = (i + 1) % count;
585 copy(fd, handle[dst], tiling[dst], handle[src], tiling[src]);
586 start_val[dst] = start_val[src];
588 printf("verifying..."); fflush(stdout);
589 for (i = 0; i < count; i++)
590 check_bo(fd, handle[i], start_val[i]);
593 printf("Random blits..."); fflush(stdout);
594 for (i = 0; i < count * 32; i++) {
595 int src = random() % count;
596 int dst = random() % count;
599 dst = random() % count;
601 copy(fd, handle[dst], tiling[dst], handle[src], tiling[src]);
602 start_val[dst] = start_val[src];
604 printf("verifying..."); fflush(stdout);
605 for (i = 0; i < count; i++)
606 check_bo(fd, handle[i], start_val[i]);