2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Chris Wilson <chris@chris-wilson.co.uk>
28 /** @file gen3_linear_render_blits.c
30 * This is a test of doing many blits, with a working set
31 * larger than the aperture size.
33 * The goal is to simply ensure the basics work.
46 #include <sys/ioctl.h>
50 #include "intel_gpu_tools.h"
58 static inline uint32_t pack_float(float f)
68 static uint32_t gem_create(int fd, int size)
70 struct drm_i915_gem_create create;
74 (void)drmIoctl(fd, DRM_IOCTL_I915_GEM_CREATE, &create);
75 assert(create.handle);
81 gem_aperture_size(int fd)
83 struct drm_i915_gem_get_aperture aperture;
85 aperture.aper_size = 512*1024*1024;
86 (void)drmIoctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
87 return aperture.aper_size;
91 gem_write(int fd, uint32_t handle, int offset, int size, const void *buf)
93 struct drm_i915_gem_pwrite pwrite;
96 pwrite.handle = handle;
97 pwrite.offset = offset;
99 pwrite.data_ptr = (uintptr_t)buf;
100 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_PWRITE, &pwrite);
104 static uint32_t fill_reloc(struct drm_i915_gem_relocation_entry *reloc,
107 uint32_t read_domain,
108 uint32_t write_domain)
110 reloc->target_handle = handle;
112 reloc->offset = offset * sizeof(uint32_t);
113 reloc->presumed_offset = 0;
114 reloc->read_domains = read_domain;
115 reloc->write_domain = write_domain;
117 return reloc->presumed_offset + reloc->delta;
122 uint32_t dst, int dst_tiling,
123 uint32_t src, int src_tiling,
126 uint32_t batch[1024], *b = batch;
127 struct drm_i915_gem_relocation_entry reloc[2], *r = reloc;
128 struct drm_i915_gem_exec_object2 obj[3];
129 struct drm_i915_gem_execbuffer2 exec;
131 uint32_t tiling_bits;
134 /* invariant state */
135 *b++ = (_3DSTATE_AA_CMD |
136 AA_LINE_ECAAR_WIDTH_ENABLE |
137 AA_LINE_ECAAR_WIDTH_1_0 |
138 AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
139 *b++ = (_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD |
141 IAB_MODIFY_FUNC | (BLENDFUNC_ADD << IAB_FUNC_SHIFT) |
142 IAB_MODIFY_SRC_FACTOR |
143 (BLENDFACT_ONE << IAB_SRC_FACTOR_SHIFT) |
144 IAB_MODIFY_DST_FACTOR |
145 (BLENDFACT_ZERO << IAB_DST_FACTOR_SHIFT));
146 *b++ = (_3DSTATE_DFLT_DIFFUSE_CMD);
148 *b++ = (_3DSTATE_DFLT_SPEC_CMD);
150 *b++ = (_3DSTATE_DFLT_Z_CMD);
152 *b++ = (_3DSTATE_COORD_SET_BINDINGS |
161 *b++ = (_3DSTATE_RASTER_RULES_CMD |
162 ENABLE_POINT_RASTER_RULE |
163 OGL_POINT_RASTER_RULE |
164 ENABLE_LINE_STRIP_PROVOKE_VRTX |
165 ENABLE_TRI_FAN_PROVOKE_VRTX |
166 LINE_STRIP_PROVOKE_VRTX(1) |
167 TRI_FAN_PROVOKE_VRTX(2) |
168 ENABLE_TEXKILL_3D_4D |
170 *b++ = (_3DSTATE_MODES_4_CMD |
171 ENABLE_LOGIC_OP_FUNC | LOGIC_OP_FUNC(LOGICOP_COPY) |
172 ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff) |
173 ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff));
174 *b++ = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | I1_LOAD_S(4) | I1_LOAD_S(5) | 2);
175 *b++ = (0x00000000); /* Disable texture coordinate wrap-shortest */
176 *b++ = ((1 << S4_POINT_WIDTH_SHIFT) |
180 *b++ = (0x00000000); /* Stencil. */
181 *b++ = (_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
182 *b++ = (_3DSTATE_SCISSOR_RECT_0_CMD);
185 *b++ = (_3DSTATE_DEPTH_SUBRECT_DISABLE);
186 *b++ = (_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
188 *b++ = (_3DSTATE_STIPPLE);
190 *b++ = (_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0);
194 tiling_bits = MS3_USE_FENCE_REGS;
197 if (src_tiling != I915_TILING_NONE)
198 tiling_bits = MS3_TILED_SURFACE;
199 if (src_tiling == I915_TILING_Y)
200 tiling_bits |= MS3_TILE_WALK;
204 *b++ = (_3DSTATE_MAP_STATE | (3 * TEX_COUNT));
205 *b++ = ((1 << TEX_COUNT) - 1);
206 *b = fill_reloc(r++, b-batch, src, I915_GEM_DOMAIN_SAMPLER, 0); b++;
207 *b++ = (MAPSURF_32BIT | MT_32BIT_ARGB8888 | tiling_bits |
208 (HEIGHT - 1) << MS3_HEIGHT_SHIFT |
209 (WIDTH - 1) << MS3_WIDTH_SHIFT);
210 *b++ = ((WIDTH-1) << MS4_PITCH_SHIFT);
212 *b++ = (_3DSTATE_SAMPLER_STATE | (3 * TEX_COUNT));
213 *b++ = ((1 << TEX_COUNT) - 1);
214 *b++ = (MIPFILTER_NONE << SS2_MIP_FILTER_SHIFT |
215 FILTER_NEAREST << SS2_MAG_FILTER_SHIFT |
216 FILTER_NEAREST << SS2_MIN_FILTER_SHIFT);
217 *b++ = (TEXCOORDMODE_WRAP << SS3_TCX_ADDR_MODE_SHIFT |
218 TEXCOORDMODE_WRAP << SS3_TCY_ADDR_MODE_SHIFT |
219 0 << SS3_TEXTUREMAP_INDEX_SHIFT);
222 /* render target state */
224 tiling_bits = BUF_3D_USE_FENCE;
227 if (dst_tiling != I915_TILING_NONE)
228 tiling_bits = BUF_3D_TILED_SURFACE;
229 if (dst_tiling == I915_TILING_Y)
230 tiling_bits |= BUF_3D_TILE_WALK_Y;
232 *b++ = (_3DSTATE_BUF_INFO_CMD);
233 *b++ = (BUF_3D_ID_COLOR_BACK | tiling_bits | WIDTH*4);
234 *b = fill_reloc(r++, b-batch, dst,
235 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
238 *b++ = (_3DSTATE_DST_BUF_VARS_CMD);
239 *b++ = (COLR_BUF_ARGB8888 |
240 DSTORG_HORT_BIAS(0x8) |
241 DSTORG_VERT_BIAS(0x8));
243 /* draw rect is unconditional */
244 *b++ = (_3DSTATE_DRAW_RECT_CMD);
246 *b++ = (0x00000000); /* ymin, xmin */
247 *b++ = (DRAW_YMAX(HEIGHT - 1) |
248 DRAW_XMAX(WIDTH - 1));
249 /* yorig, xorig (relate to color buffer?) */
253 *b++ = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(1) | I1_LOAD_S(2) | I1_LOAD_S(6) | 2);
254 *b++ = ((4 << S1_VERTEX_WIDTH_SHIFT) | (4 << S1_VERTEX_PITCH_SHIFT));
255 *b++ = (~S2_TEXCOORD_FMT(0, TEXCOORDFMT_NOT_PRESENT) |
256 S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D));
257 *b++ = (S6_CBUF_BLEND_ENABLE | S6_COLOR_WRITE_ENABLE |
258 BLENDFUNC_ADD << S6_CBUF_BLEND_FUNC_SHIFT |
259 BLENDFACT_ONE << S6_CBUF_SRC_BLEND_FACT_SHIFT |
260 BLENDFACT_ZERO << S6_CBUF_DST_BLEND_FACT_SHIFT);
263 *b++ = (_3DSTATE_PIXEL_SHADER_PROGRAM | (1 + 3*3 - 2));
266 REG_TYPE(FS_T0) << D0_TYPE_SHIFT |
267 REG_NR(FS_T0) << D0_NR_SHIFT |
268 ((REG_TYPE(FS_T0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0));
273 (REG_TYPE(FS_S0) << D0_TYPE_SHIFT) |
274 (REG_NR(FS_S0) << D0_NR_SHIFT) |
275 ((REG_TYPE(FS_S0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0));
278 /* texld(FS_OC, FS_S0, FS_T0 */
280 (REG_TYPE(FS_OC) << T0_DEST_TYPE_SHIFT) |
281 (REG_NR(FS_OC) << T0_DEST_NR_SHIFT) |
282 (REG_NR(FS_S0) << T0_SAMPLER_NR_SHIFT));
283 *b++ = ((REG_TYPE(FS_T0) << T1_ADDRESS_REG_TYPE_SHIFT) |
284 (REG_NR(FS_T0) << T1_ADDRESS_REG_NR_SHIFT));
287 *b++ = (PRIM3D_RECTLIST | (3*4 - 1));
288 *b++ = pack_float(WIDTH);
289 *b++ = pack_float(HEIGHT);
290 *b++ = pack_float(WIDTH);
291 *b++ = pack_float(HEIGHT);
293 *b++ = pack_float(0);
294 *b++ = pack_float(HEIGHT);
295 *b++ = pack_float(0);
296 *b++ = pack_float(HEIGHT);
298 *b++ = pack_float(0);
299 *b++ = pack_float(0);
300 *b++ = pack_float(0);
301 *b++ = pack_float(0);
303 *b++ = MI_BATCH_BUFFER_END;
307 assert(b - batch <= 1024);
308 handle = gem_create(fd, 4096);
309 gem_write(fd, handle, 0, (b-batch)*sizeof(batch[0]), batch);
311 assert(r-reloc == 2);
315 tiling_bits = EXEC_OBJECT_NEEDS_FENCE;
318 obj[0].relocation_count = 0;
319 obj[0].relocs_ptr = 0;
320 obj[0].alignment = 0;
322 obj[0].flags = tiling_bits;
327 obj[1].relocation_count = 0;
328 obj[1].relocs_ptr = 0;
329 obj[1].alignment = 0;
331 obj[1].flags = tiling_bits;
335 obj[2].handle = handle;
336 obj[2].relocation_count = 2;
337 obj[2].relocs_ptr = (uintptr_t)reloc;
338 obj[2].alignment = 0;
341 obj[2].rsvd1 = obj[2].rsvd2 = 0;
343 exec.buffers_ptr = (uintptr_t)obj;
344 exec.buffer_count = 3;
345 exec.batch_start_offset = 0;
346 exec.batch_len = (b-batch)*sizeof(batch[0]);
347 exec.DR1 = exec.DR4 = 0;
348 exec.num_cliprects = 0;
349 exec.cliprects_ptr = 0;
351 exec.rsvd1 = exec.rsvd2 = 0;
353 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
354 while (ret && errno == EBUSY) {
355 drmCommandNone(fd, DRM_I915_GEM_THROTTLE);
356 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
360 gem_close(fd, handle);
363 static void blt_copy(int fd, uint32_t dst, uint32_t src)
365 uint32_t batch[1024], *b = batch;
366 struct drm_i915_gem_relocation_entry reloc[2], *r = reloc;
367 struct drm_i915_gem_exec_object2 obj[3];
368 struct drm_i915_gem_execbuffer2 exec;
372 *b++ = (XY_SRC_COPY_BLT_CMD |
373 XY_SRC_COPY_BLT_WRITE_ALPHA |
374 XY_SRC_COPY_BLT_WRITE_RGB);
375 *b++ = 3 << 24 | 0xcc << 16 | WIDTH * 4;
377 *b++ = HEIGHT << 16 | WIDTH;
378 *b = fill_reloc(r++, b-batch, dst,
379 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER); b++;
382 *b = fill_reloc(r++, b-batch, src, I915_GEM_DOMAIN_RENDER, 0); b++;
384 *b++ = MI_BATCH_BUFFER_END;
388 assert(b - batch <= 1024);
389 handle = gem_create(fd, 4096);
390 gem_write(fd, handle, 0, (b-batch)*sizeof(batch[0]), batch);
392 assert(r-reloc == 2);
395 obj[0].relocation_count = 0;
396 obj[0].relocs_ptr = 0;
397 obj[0].alignment = 0;
399 obj[0].flags = EXEC_OBJECT_NEEDS_FENCE;
404 obj[1].relocation_count = 0;
405 obj[1].relocs_ptr = 0;
406 obj[1].alignment = 0;
408 obj[1].flags = EXEC_OBJECT_NEEDS_FENCE;
412 obj[2].handle = handle;
413 obj[2].relocation_count = 2;
414 obj[2].relocs_ptr = (uintptr_t)reloc;
415 obj[2].alignment = 0;
418 obj[2].rsvd1 = obj[2].rsvd2 = 0;
420 exec.buffers_ptr = (uintptr_t)obj;
421 exec.buffer_count = 3;
422 exec.batch_start_offset = 0;
423 exec.batch_len = (b-batch)*sizeof(batch[0]);
424 exec.DR1 = exec.DR4 = 0;
425 exec.num_cliprects = 0;
426 exec.cliprects_ptr = 0;
428 exec.rsvd1 = exec.rsvd2 = 0;
430 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
431 while (ret && errno == EBUSY) {
432 drmCommandNone(fd, DRM_I915_GEM_THROTTLE);
433 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
437 gem_close(fd, handle);
443 uint32_t dst, int dst_tiling,
444 uint32_t src, int src_tiling)
447 switch (random() % 3) {
448 case 0: render_copy(fd, dst, dst_tiling, src, src_tiling, 0); break;
449 case 1: render_copy(fd, dst, dst_tiling, src, src_tiling, 1); break;
450 case 2: if (dst_tiling == I915_TILING_Y || src_tiling == I915_TILING_Y)
452 blt_copy(fd, dst, src);
457 static void *gem_mmap(int fd, uint32_t handle, int size, int prot)
459 struct drm_i915_gem_mmap_gtt mmap_arg;
462 mmap_arg.handle = handle;
463 if (drmIoctl(fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &mmap_arg)) {
468 ptr = mmap(0, size, prot, MAP_SHARED, fd, mmap_arg.offset);
469 if (ptr == MAP_FAILED) {
478 create_bo(int fd, uint32_t val, int tiling)
484 handle = gem_create(fd, WIDTH*HEIGHT*4);
485 gem_set_tiling(fd, handle, tiling, WIDTH*4);
487 /* Fill the BO with dwords starting at val */
488 v = gem_mmap(fd, handle, WIDTH*HEIGHT*4, PROT_READ | PROT_WRITE);
489 for (i = 0; i < WIDTH*HEIGHT; i++)
491 munmap(v, WIDTH*HEIGHT*4);
497 check_bo(int fd, uint32_t handle, uint32_t val)
502 v = gem_mmap(fd, handle, WIDTH*HEIGHT*4, PROT_READ);
503 for (i = 0; i < WIDTH*HEIGHT; i++) {
505 fprintf(stderr, "Expected 0x%08x, found 0x%08x "
506 "at offset 0x%08x\n",
512 munmap(v, WIDTH*HEIGHT*4);
515 int main(int argc, char **argv)
517 uint32_t *handle, *tiling, *start_val;
523 if (!IS_GEN3(intel_get_drm_devid(fd))) {
524 printf("gen3-only test, doing nothing\n");
530 count = atoi(argv[1]);
532 count = 3 * gem_aperture_size(fd) / (1024*1024) / 2;
533 printf("Using %d 1MiB buffers\n", count);
535 handle = malloc(sizeof(uint32_t)*count*3);
536 tiling = handle + count;
537 start_val = tiling + count;
539 for (i = 0; i < count; i++) {
540 handle[i] = create_bo(fd, start, tiling[i] = i % 3);
541 start_val[i] = start;
542 start += 1024 * 1024 / 4;
545 printf("Verifying initialisation..."); fflush(stdout);
546 for (i = 0; i < count; i++)
547 check_bo(fd, handle[i], start_val[i]);
550 printf("Cyclic blits, forward..."); fflush(stdout);
551 for (i = 0; i < count * 32; i++) {
553 int dst = (i + 1) % count;
555 copy(fd, handle[dst], tiling[dst], handle[src], tiling[src]);
556 start_val[dst] = start_val[src];
558 printf("verifying..."); fflush(stdout);
559 for (i = 0; i < count; i++)
560 check_bo(fd, handle[i], start_val[i]);
563 printf("Cyclic blits, backward..."); fflush(stdout);
564 for (i = 0; i < count * 32; i++) {
565 int src = (i + 1) % count;
568 copy(fd, handle[dst], tiling[dst], handle[src], tiling[src]);
569 start_val[dst] = start_val[src];
571 printf("verifying..."); fflush(stdout);
572 for (i = 0; i < count; i++)
573 check_bo(fd, handle[i], start_val[i]);
576 printf("Random blits..."); fflush(stdout);
577 for (i = 0; i < count * 32; i++) {
578 int src = random() % count;
579 int dst = random() % count;
582 dst = random() % count;
584 copy(fd, handle[dst], tiling[dst], handle[src], tiling[src]);
585 start_val[dst] = start_val[src];
587 printf("verifying..."); fflush(stdout);
588 for (i = 0; i < count; i++)
589 check_bo(fd, handle[i], start_val[i]);