2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Chris Wilson <chris@chris-wilson.co.uk>
28 /** @file gen3_linear_render_blits.c
30 * This is a test of doing many blits, with a working set
31 * larger than the aperture size.
33 * The goal is to simply ensure the basics work.
46 #include <sys/ioctl.h>
50 #include "intel_gpu_tools.h"
58 static inline uint32_t pack_float(float f)
68 static uint32_t gem_create(int fd, int size)
70 struct drm_i915_gem_create create;
74 (void)drmIoctl(fd, DRM_IOCTL_I915_GEM_CREATE, &create);
75 assert(create.handle);
81 gem_aperture_size(int fd)
83 struct drm_i915_gem_get_aperture aperture;
85 aperture.aper_size = 512*1024*1024;
86 (void)drmIoctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
87 return aperture.aper_size;
90 static uint32_t fill_reloc(struct drm_i915_gem_relocation_entry *reloc,
94 uint32_t write_domain)
96 reloc->target_handle = handle;
98 reloc->offset = offset * sizeof(uint32_t);
99 reloc->presumed_offset = 0;
100 reloc->read_domains = read_domain;
101 reloc->write_domain = write_domain;
103 return reloc->presumed_offset + reloc->delta;
108 uint32_t dst, int dst_tiling,
109 uint32_t src, int src_tiling,
112 uint32_t batch[1024], *b = batch;
113 struct drm_i915_gem_relocation_entry reloc[2], *r = reloc;
114 struct drm_i915_gem_exec_object2 obj[3];
115 struct drm_i915_gem_execbuffer2 exec;
117 uint32_t tiling_bits;
120 /* invariant state */
121 *b++ = (_3DSTATE_AA_CMD |
122 AA_LINE_ECAAR_WIDTH_ENABLE |
123 AA_LINE_ECAAR_WIDTH_1_0 |
124 AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
125 *b++ = (_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD |
127 IAB_MODIFY_FUNC | (BLENDFUNC_ADD << IAB_FUNC_SHIFT) |
128 IAB_MODIFY_SRC_FACTOR |
129 (BLENDFACT_ONE << IAB_SRC_FACTOR_SHIFT) |
130 IAB_MODIFY_DST_FACTOR |
131 (BLENDFACT_ZERO << IAB_DST_FACTOR_SHIFT));
132 *b++ = (_3DSTATE_DFLT_DIFFUSE_CMD);
134 *b++ = (_3DSTATE_DFLT_SPEC_CMD);
136 *b++ = (_3DSTATE_DFLT_Z_CMD);
138 *b++ = (_3DSTATE_COORD_SET_BINDINGS |
147 *b++ = (_3DSTATE_RASTER_RULES_CMD |
148 ENABLE_POINT_RASTER_RULE |
149 OGL_POINT_RASTER_RULE |
150 ENABLE_LINE_STRIP_PROVOKE_VRTX |
151 ENABLE_TRI_FAN_PROVOKE_VRTX |
152 LINE_STRIP_PROVOKE_VRTX(1) |
153 TRI_FAN_PROVOKE_VRTX(2) |
154 ENABLE_TEXKILL_3D_4D |
156 *b++ = (_3DSTATE_MODES_4_CMD |
157 ENABLE_LOGIC_OP_FUNC | LOGIC_OP_FUNC(LOGICOP_COPY) |
158 ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff) |
159 ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff));
160 *b++ = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | I1_LOAD_S(4) | I1_LOAD_S(5) | 2);
161 *b++ = (0x00000000); /* Disable texture coordinate wrap-shortest */
162 *b++ = ((1 << S4_POINT_WIDTH_SHIFT) |
166 *b++ = (0x00000000); /* Stencil. */
167 *b++ = (_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
168 *b++ = (_3DSTATE_SCISSOR_RECT_0_CMD);
171 *b++ = (_3DSTATE_DEPTH_SUBRECT_DISABLE);
172 *b++ = (_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
174 *b++ = (_3DSTATE_STIPPLE);
176 *b++ = (_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0);
180 tiling_bits = MS3_USE_FENCE_REGS;
183 if (src_tiling != I915_TILING_NONE)
184 tiling_bits = MS3_TILED_SURFACE;
185 if (src_tiling == I915_TILING_Y)
186 tiling_bits |= MS3_TILE_WALK;
190 *b++ = (_3DSTATE_MAP_STATE | (3 * TEX_COUNT));
191 *b++ = ((1 << TEX_COUNT) - 1);
192 *b = fill_reloc(r++, b-batch, src, I915_GEM_DOMAIN_SAMPLER, 0); b++;
193 *b++ = (MAPSURF_32BIT | MT_32BIT_ARGB8888 | tiling_bits |
194 (HEIGHT - 1) << MS3_HEIGHT_SHIFT |
195 (WIDTH - 1) << MS3_WIDTH_SHIFT);
196 *b++ = ((WIDTH-1) << MS4_PITCH_SHIFT);
198 *b++ = (_3DSTATE_SAMPLER_STATE | (3 * TEX_COUNT));
199 *b++ = ((1 << TEX_COUNT) - 1);
200 *b++ = (MIPFILTER_NONE << SS2_MIP_FILTER_SHIFT |
201 FILTER_NEAREST << SS2_MAG_FILTER_SHIFT |
202 FILTER_NEAREST << SS2_MIN_FILTER_SHIFT);
203 *b++ = (TEXCOORDMODE_WRAP << SS3_TCX_ADDR_MODE_SHIFT |
204 TEXCOORDMODE_WRAP << SS3_TCY_ADDR_MODE_SHIFT |
205 0 << SS3_TEXTUREMAP_INDEX_SHIFT);
208 /* render target state */
210 tiling_bits = BUF_3D_USE_FENCE;
213 if (dst_tiling != I915_TILING_NONE)
214 tiling_bits = BUF_3D_TILED_SURFACE;
215 if (dst_tiling == I915_TILING_Y)
216 tiling_bits |= BUF_3D_TILE_WALK_Y;
218 *b++ = (_3DSTATE_BUF_INFO_CMD);
219 *b++ = (BUF_3D_ID_COLOR_BACK | tiling_bits | WIDTH*4);
220 *b = fill_reloc(r++, b-batch, dst,
221 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
224 *b++ = (_3DSTATE_DST_BUF_VARS_CMD);
225 *b++ = (COLR_BUF_ARGB8888 |
226 DSTORG_HORT_BIAS(0x8) |
227 DSTORG_VERT_BIAS(0x8));
229 /* draw rect is unconditional */
230 *b++ = (_3DSTATE_DRAW_RECT_CMD);
232 *b++ = (0x00000000); /* ymin, xmin */
233 *b++ = (DRAW_YMAX(HEIGHT - 1) |
234 DRAW_XMAX(WIDTH - 1));
235 /* yorig, xorig (relate to color buffer?) */
239 *b++ = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(1) | I1_LOAD_S(2) | I1_LOAD_S(6) | 2);
240 *b++ = ((4 << S1_VERTEX_WIDTH_SHIFT) | (4 << S1_VERTEX_PITCH_SHIFT));
241 *b++ = (~S2_TEXCOORD_FMT(0, TEXCOORDFMT_NOT_PRESENT) |
242 S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D));
243 *b++ = (S6_CBUF_BLEND_ENABLE | S6_COLOR_WRITE_ENABLE |
244 BLENDFUNC_ADD << S6_CBUF_BLEND_FUNC_SHIFT |
245 BLENDFACT_ONE << S6_CBUF_SRC_BLEND_FACT_SHIFT |
246 BLENDFACT_ZERO << S6_CBUF_DST_BLEND_FACT_SHIFT);
249 *b++ = (_3DSTATE_PIXEL_SHADER_PROGRAM | (1 + 3*3 - 2));
252 REG_TYPE(FS_T0) << D0_TYPE_SHIFT |
253 REG_NR(FS_T0) << D0_NR_SHIFT |
254 ((REG_TYPE(FS_T0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0));
259 (REG_TYPE(FS_S0) << D0_TYPE_SHIFT) |
260 (REG_NR(FS_S0) << D0_NR_SHIFT) |
261 ((REG_TYPE(FS_S0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0));
264 /* texld(FS_OC, FS_S0, FS_T0 */
266 (REG_TYPE(FS_OC) << T0_DEST_TYPE_SHIFT) |
267 (REG_NR(FS_OC) << T0_DEST_NR_SHIFT) |
268 (REG_NR(FS_S0) << T0_SAMPLER_NR_SHIFT));
269 *b++ = ((REG_TYPE(FS_T0) << T1_ADDRESS_REG_TYPE_SHIFT) |
270 (REG_NR(FS_T0) << T1_ADDRESS_REG_NR_SHIFT));
273 *b++ = (PRIM3D_RECTLIST | (3*4 - 1));
274 *b++ = pack_float(WIDTH);
275 *b++ = pack_float(HEIGHT);
276 *b++ = pack_float(WIDTH);
277 *b++ = pack_float(HEIGHT);
279 *b++ = pack_float(0);
280 *b++ = pack_float(HEIGHT);
281 *b++ = pack_float(0);
282 *b++ = pack_float(HEIGHT);
284 *b++ = pack_float(0);
285 *b++ = pack_float(0);
286 *b++ = pack_float(0);
287 *b++ = pack_float(0);
289 *b++ = MI_BATCH_BUFFER_END;
293 assert(b - batch <= 1024);
294 handle = gem_create(fd, 4096);
295 gem_write(fd, handle, 0, batch, (b-batch)*sizeof(batch[0]));
297 assert(r-reloc == 2);
301 tiling_bits = EXEC_OBJECT_NEEDS_FENCE;
304 obj[0].relocation_count = 0;
305 obj[0].relocs_ptr = 0;
306 obj[0].alignment = 0;
308 obj[0].flags = tiling_bits;
313 obj[1].relocation_count = 0;
314 obj[1].relocs_ptr = 0;
315 obj[1].alignment = 0;
317 obj[1].flags = tiling_bits;
321 obj[2].handle = handle;
322 obj[2].relocation_count = 2;
323 obj[2].relocs_ptr = (uintptr_t)reloc;
324 obj[2].alignment = 0;
327 obj[2].rsvd1 = obj[2].rsvd2 = 0;
329 exec.buffers_ptr = (uintptr_t)obj;
330 exec.buffer_count = 3;
331 exec.batch_start_offset = 0;
332 exec.batch_len = (b-batch)*sizeof(batch[0]);
333 exec.DR1 = exec.DR4 = 0;
334 exec.num_cliprects = 0;
335 exec.cliprects_ptr = 0;
337 exec.rsvd1 = exec.rsvd2 = 0;
339 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
340 while (ret && errno == EBUSY) {
341 drmCommandNone(fd, DRM_I915_GEM_THROTTLE);
342 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
346 gem_close(fd, handle);
349 static void blt_copy(int fd, uint32_t dst, uint32_t src)
351 uint32_t batch[1024], *b = batch;
352 struct drm_i915_gem_relocation_entry reloc[2], *r = reloc;
353 struct drm_i915_gem_exec_object2 obj[3];
354 struct drm_i915_gem_execbuffer2 exec;
358 *b++ = (XY_SRC_COPY_BLT_CMD |
359 XY_SRC_COPY_BLT_WRITE_ALPHA |
360 XY_SRC_COPY_BLT_WRITE_RGB);
361 *b++ = 3 << 24 | 0xcc << 16 | WIDTH * 4;
363 *b++ = HEIGHT << 16 | WIDTH;
364 *b = fill_reloc(r++, b-batch, dst,
365 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER); b++;
368 *b = fill_reloc(r++, b-batch, src, I915_GEM_DOMAIN_RENDER, 0); b++;
370 *b++ = MI_BATCH_BUFFER_END;
374 assert(b - batch <= 1024);
375 handle = gem_create(fd, 4096);
376 gem_write(fd, handle, 0, batch, (b-batch)*sizeof(batch[0]));
378 assert(r-reloc == 2);
381 obj[0].relocation_count = 0;
382 obj[0].relocs_ptr = 0;
383 obj[0].alignment = 0;
385 obj[0].flags = EXEC_OBJECT_NEEDS_FENCE;
390 obj[1].relocation_count = 0;
391 obj[1].relocs_ptr = 0;
392 obj[1].alignment = 0;
394 obj[1].flags = EXEC_OBJECT_NEEDS_FENCE;
398 obj[2].handle = handle;
399 obj[2].relocation_count = 2;
400 obj[2].relocs_ptr = (uintptr_t)reloc;
401 obj[2].alignment = 0;
404 obj[2].rsvd1 = obj[2].rsvd2 = 0;
406 exec.buffers_ptr = (uintptr_t)obj;
407 exec.buffer_count = 3;
408 exec.batch_start_offset = 0;
409 exec.batch_len = (b-batch)*sizeof(batch[0]);
410 exec.DR1 = exec.DR4 = 0;
411 exec.num_cliprects = 0;
412 exec.cliprects_ptr = 0;
414 exec.rsvd1 = exec.rsvd2 = 0;
416 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
417 while (ret && errno == EBUSY) {
418 drmCommandNone(fd, DRM_I915_GEM_THROTTLE);
419 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
423 gem_close(fd, handle);
429 uint32_t dst, int dst_tiling,
430 uint32_t src, int src_tiling)
433 switch (random() % 3) {
434 case 0: render_copy(fd, dst, dst_tiling, src, src_tiling, 0); break;
435 case 1: render_copy(fd, dst, dst_tiling, src, src_tiling, 1); break;
436 case 2: if (dst_tiling == I915_TILING_Y || src_tiling == I915_TILING_Y)
438 blt_copy(fd, dst, src);
443 static void *gem_mmap(int fd, uint32_t handle, int size, int prot)
445 struct drm_i915_gem_mmap_gtt mmap_arg;
448 mmap_arg.handle = handle;
449 if (drmIoctl(fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &mmap_arg)) {
454 ptr = mmap(0, size, prot, MAP_SHARED, fd, mmap_arg.offset);
455 if (ptr == MAP_FAILED) {
464 create_bo(int fd, uint32_t val, int tiling)
470 handle = gem_create(fd, WIDTH*HEIGHT*4);
471 gem_set_tiling(fd, handle, tiling, WIDTH*4);
473 /* Fill the BO with dwords starting at val */
474 v = gem_mmap(fd, handle, WIDTH*HEIGHT*4, PROT_READ | PROT_WRITE);
475 for (i = 0; i < WIDTH*HEIGHT; i++)
477 munmap(v, WIDTH*HEIGHT*4);
483 check_bo(int fd, uint32_t handle, uint32_t val)
488 v = gem_mmap(fd, handle, WIDTH*HEIGHT*4, PROT_READ);
489 for (i = 0; i < WIDTH*HEIGHT; i++) {
491 fprintf(stderr, "Expected 0x%08x, found 0x%08x "
492 "at offset 0x%08x\n",
498 munmap(v, WIDTH*HEIGHT*4);
501 int main(int argc, char **argv)
503 uint32_t *handle, *tiling, *start_val;
509 if (!IS_GEN3(intel_get_drm_devid(fd))) {
510 printf("gen3-only test, doing nothing\n");
516 count = atoi(argv[1]);
518 count = 3 * gem_aperture_size(fd) / (1024*1024) / 2;
519 printf("Using %d 1MiB buffers\n", count);
521 handle = malloc(sizeof(uint32_t)*count*3);
522 tiling = handle + count;
523 start_val = tiling + count;
525 for (i = 0; i < count; i++) {
526 handle[i] = create_bo(fd, start, tiling[i] = i % 3);
527 start_val[i] = start;
528 start += 1024 * 1024 / 4;
531 printf("Verifying initialisation..."); fflush(stdout);
532 for (i = 0; i < count; i++)
533 check_bo(fd, handle[i], start_val[i]);
536 printf("Cyclic blits, forward..."); fflush(stdout);
537 for (i = 0; i < count * 32; i++) {
539 int dst = (i + 1) % count;
541 copy(fd, handle[dst], tiling[dst], handle[src], tiling[src]);
542 start_val[dst] = start_val[src];
544 printf("verifying..."); fflush(stdout);
545 for (i = 0; i < count; i++)
546 check_bo(fd, handle[i], start_val[i]);
549 printf("Cyclic blits, backward..."); fflush(stdout);
550 for (i = 0; i < count * 32; i++) {
551 int src = (i + 1) % count;
554 copy(fd, handle[dst], tiling[dst], handle[src], tiling[src]);
555 start_val[dst] = start_val[src];
557 printf("verifying..."); fflush(stdout);
558 for (i = 0; i < count; i++)
559 check_bo(fd, handle[i], start_val[i]);
562 printf("Random blits..."); fflush(stdout);
563 for (i = 0; i < count * 32; i++) {
564 int src = random() % count;
565 int dst = random() % count;
568 dst = random() % count;
570 copy(fd, handle[dst], tiling[dst], handle[src], tiling[src]);
571 start_val[dst] = start_val[src];
573 printf("verifying..."); fflush(stdout);
574 for (i = 0; i < count; i++)
575 check_bo(fd, handle[i], start_val[i]);