2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Chris Wilson <chris@chris-wilson.co.uk>
28 /** @file gen3_linear_render_blits.c
30 * This is a test of doing many blits, with a working set
31 * larger than the aperture size.
33 * The goal is to simply ensure the basics work.
44 #include <sys/ioctl.h>
46 #include "ioctl_wrappers.h"
49 #include "intel_chipset.h"
57 static inline uint32_t pack_float(float f)
67 static uint32_t fill_reloc(struct drm_i915_gem_relocation_entry *reloc,
71 uint32_t write_domain)
73 reloc->target_handle = handle;
75 reloc->offset = offset * sizeof(uint32_t);
76 reloc->presumed_offset = 0;
77 reloc->read_domains = read_domain;
78 reloc->write_domain = write_domain;
80 return reloc->presumed_offset + reloc->delta;
85 uint32_t dst, int dst_tiling,
86 uint32_t src, int src_tiling,
89 uint32_t batch[1024], *b = batch;
90 struct drm_i915_gem_relocation_entry reloc[2], *r = reloc;
91 struct drm_i915_gem_exec_object2 obj[3];
92 struct drm_i915_gem_execbuffer2 exec;
98 *b++ = (_3DSTATE_AA_CMD |
99 AA_LINE_ECAAR_WIDTH_ENABLE |
100 AA_LINE_ECAAR_WIDTH_1_0 |
101 AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
102 *b++ = (_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD |
104 IAB_MODIFY_FUNC | (BLENDFUNC_ADD << IAB_FUNC_SHIFT) |
105 IAB_MODIFY_SRC_FACTOR |
106 (BLENDFACT_ONE << IAB_SRC_FACTOR_SHIFT) |
107 IAB_MODIFY_DST_FACTOR |
108 (BLENDFACT_ZERO << IAB_DST_FACTOR_SHIFT));
109 *b++ = (_3DSTATE_DFLT_DIFFUSE_CMD);
111 *b++ = (_3DSTATE_DFLT_SPEC_CMD);
113 *b++ = (_3DSTATE_DFLT_Z_CMD);
115 *b++ = (_3DSTATE_COORD_SET_BINDINGS |
124 *b++ = (_3DSTATE_RASTER_RULES_CMD |
125 ENABLE_POINT_RASTER_RULE |
126 OGL_POINT_RASTER_RULE |
127 ENABLE_LINE_STRIP_PROVOKE_VRTX |
128 ENABLE_TRI_FAN_PROVOKE_VRTX |
129 LINE_STRIP_PROVOKE_VRTX(1) |
130 TRI_FAN_PROVOKE_VRTX(2) |
131 ENABLE_TEXKILL_3D_4D |
133 *b++ = (_3DSTATE_MODES_4_CMD |
134 ENABLE_LOGIC_OP_FUNC | LOGIC_OP_FUNC(LOGICOP_COPY) |
135 ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff) |
136 ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff));
137 *b++ = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | I1_LOAD_S(4) | I1_LOAD_S(5) | 2);
138 *b++ = (0x00000000); /* Disable texture coordinate wrap-shortest */
139 *b++ = ((1 << S4_POINT_WIDTH_SHIFT) |
143 *b++ = (0x00000000); /* Stencil. */
144 *b++ = (_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
145 *b++ = (_3DSTATE_SCISSOR_RECT_0_CMD);
148 *b++ = (_3DSTATE_DEPTH_SUBRECT_DISABLE);
149 *b++ = (_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
151 *b++ = (_3DSTATE_STIPPLE);
153 *b++ = (_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0);
157 tiling_bits = MS3_USE_FENCE_REGS;
160 if (src_tiling != I915_TILING_NONE)
161 tiling_bits = MS3_TILED_SURFACE;
162 if (src_tiling == I915_TILING_Y)
163 tiling_bits |= MS3_TILE_WALK;
167 *b++ = (_3DSTATE_MAP_STATE | (3 * TEX_COUNT));
168 *b++ = ((1 << TEX_COUNT) - 1);
169 *b = fill_reloc(r++, b-batch, src, I915_GEM_DOMAIN_SAMPLER, 0); b++;
170 *b++ = (MAPSURF_32BIT | MT_32BIT_ARGB8888 | tiling_bits |
171 (HEIGHT - 1) << MS3_HEIGHT_SHIFT |
172 (WIDTH - 1) << MS3_WIDTH_SHIFT);
173 *b++ = ((WIDTH-1) << MS4_PITCH_SHIFT);
175 *b++ = (_3DSTATE_SAMPLER_STATE | (3 * TEX_COUNT));
176 *b++ = ((1 << TEX_COUNT) - 1);
177 *b++ = (MIPFILTER_NONE << SS2_MIP_FILTER_SHIFT |
178 FILTER_NEAREST << SS2_MAG_FILTER_SHIFT |
179 FILTER_NEAREST << SS2_MIN_FILTER_SHIFT);
180 *b++ = (TEXCOORDMODE_WRAP << SS3_TCX_ADDR_MODE_SHIFT |
181 TEXCOORDMODE_WRAP << SS3_TCY_ADDR_MODE_SHIFT |
182 0 << SS3_TEXTUREMAP_INDEX_SHIFT);
185 /* render target state */
187 tiling_bits = BUF_3D_USE_FENCE;
190 if (dst_tiling != I915_TILING_NONE)
191 tiling_bits = BUF_3D_TILED_SURFACE;
192 if (dst_tiling == I915_TILING_Y)
193 tiling_bits |= BUF_3D_TILE_WALK_Y;
195 *b++ = (_3DSTATE_BUF_INFO_CMD);
196 *b++ = (BUF_3D_ID_COLOR_BACK | tiling_bits | WIDTH*4);
197 *b = fill_reloc(r++, b-batch, dst,
198 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
201 *b++ = (_3DSTATE_DST_BUF_VARS_CMD);
202 *b++ = (COLR_BUF_ARGB8888 |
203 DSTORG_HORT_BIAS(0x8) |
204 DSTORG_VERT_BIAS(0x8));
206 /* draw rect is unconditional */
207 *b++ = (_3DSTATE_DRAW_RECT_CMD);
209 *b++ = (0x00000000); /* ymin, xmin */
210 *b++ = (DRAW_YMAX(HEIGHT - 1) |
211 DRAW_XMAX(WIDTH - 1));
212 /* yorig, xorig (relate to color buffer?) */
216 *b++ = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(1) | I1_LOAD_S(2) | I1_LOAD_S(6) | 2);
217 *b++ = ((4 << S1_VERTEX_WIDTH_SHIFT) | (4 << S1_VERTEX_PITCH_SHIFT));
218 *b++ = (~S2_TEXCOORD_FMT(0, TEXCOORDFMT_NOT_PRESENT) |
219 S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D));
220 *b++ = (S6_CBUF_BLEND_ENABLE | S6_COLOR_WRITE_ENABLE |
221 BLENDFUNC_ADD << S6_CBUF_BLEND_FUNC_SHIFT |
222 BLENDFACT_ONE << S6_CBUF_SRC_BLEND_FACT_SHIFT |
223 BLENDFACT_ZERO << S6_CBUF_DST_BLEND_FACT_SHIFT);
226 *b++ = (_3DSTATE_PIXEL_SHADER_PROGRAM | (1 + 3*3 - 2));
229 REG_TYPE(FS_T0) << D0_TYPE_SHIFT |
230 REG_NR(FS_T0) << D0_NR_SHIFT |
231 ((REG_TYPE(FS_T0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0));
236 (REG_TYPE(FS_S0) << D0_TYPE_SHIFT) |
237 (REG_NR(FS_S0) << D0_NR_SHIFT) |
238 ((REG_TYPE(FS_S0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0));
241 /* texld(FS_OC, FS_S0, FS_T0 */
243 (REG_TYPE(FS_OC) << T0_DEST_TYPE_SHIFT) |
244 (REG_NR(FS_OC) << T0_DEST_NR_SHIFT) |
245 (REG_NR(FS_S0) << T0_SAMPLER_NR_SHIFT));
246 *b++ = ((REG_TYPE(FS_T0) << T1_ADDRESS_REG_TYPE_SHIFT) |
247 (REG_NR(FS_T0) << T1_ADDRESS_REG_NR_SHIFT));
250 *b++ = (PRIM3D_RECTLIST | (3*4 - 1));
251 *b++ = pack_float(WIDTH);
252 *b++ = pack_float(HEIGHT);
253 *b++ = pack_float(WIDTH);
254 *b++ = pack_float(HEIGHT);
256 *b++ = pack_float(0);
257 *b++ = pack_float(HEIGHT);
258 *b++ = pack_float(0);
259 *b++ = pack_float(HEIGHT);
261 *b++ = pack_float(0);
262 *b++ = pack_float(0);
263 *b++ = pack_float(0);
264 *b++ = pack_float(0);
266 *b++ = MI_BATCH_BUFFER_END;
270 igt_assert(b - batch <= 1024);
271 handle = gem_create(fd, 4096);
272 gem_write(fd, handle, 0, batch, (b-batch)*sizeof(batch[0]));
274 igt_assert(r-reloc == 2);
278 tiling_bits = EXEC_OBJECT_NEEDS_FENCE;
281 obj[0].relocation_count = 0;
282 obj[0].relocs_ptr = 0;
283 obj[0].alignment = 0;
285 obj[0].flags = tiling_bits;
290 obj[1].relocation_count = 0;
291 obj[1].relocs_ptr = 0;
292 obj[1].alignment = 0;
294 obj[1].flags = tiling_bits;
298 obj[2].handle = handle;
299 obj[2].relocation_count = 2;
300 obj[2].relocs_ptr = (uintptr_t)reloc;
301 obj[2].alignment = 0;
304 obj[2].rsvd1 = obj[2].rsvd2 = 0;
306 exec.buffers_ptr = (uintptr_t)obj;
307 exec.buffer_count = 3;
308 exec.batch_start_offset = 0;
309 exec.batch_len = (b-batch)*sizeof(batch[0]);
310 exec.DR1 = exec.DR4 = 0;
311 exec.num_cliprects = 0;
312 exec.cliprects_ptr = 0;
314 i915_execbuffer2_set_context_id(exec, 0);
317 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
318 while (ret && errno == EBUSY) {
319 drmCommandNone(fd, DRM_I915_GEM_THROTTLE);
320 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
322 igt_assert(ret == 0);
324 gem_close(fd, handle);
327 static void blt_copy(int fd, uint32_t dst, uint32_t src)
329 uint32_t batch[1024], *b = batch;
330 struct drm_i915_gem_relocation_entry reloc[2], *r = reloc;
331 struct drm_i915_gem_exec_object2 obj[3];
332 struct drm_i915_gem_execbuffer2 exec;
336 *b++ = (XY_SRC_COPY_BLT_CMD |
337 XY_SRC_COPY_BLT_WRITE_ALPHA |
338 XY_SRC_COPY_BLT_WRITE_RGB | 6);
339 *b++ = 3 << 24 | 0xcc << 16 | WIDTH * 4;
341 *b++ = HEIGHT << 16 | WIDTH;
342 *b = fill_reloc(r++, b-batch, dst,
343 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER); b++;
346 *b = fill_reloc(r++, b-batch, src, I915_GEM_DOMAIN_RENDER, 0); b++;
348 *b++ = MI_BATCH_BUFFER_END;
352 igt_assert(b - batch <= 1024);
353 handle = gem_create(fd, 4096);
354 gem_write(fd, handle, 0, batch, (b-batch)*sizeof(batch[0]));
356 igt_assert(r-reloc == 2);
359 obj[0].relocation_count = 0;
360 obj[0].relocs_ptr = 0;
361 obj[0].alignment = 0;
363 obj[0].flags = EXEC_OBJECT_NEEDS_FENCE;
368 obj[1].relocation_count = 0;
369 obj[1].relocs_ptr = 0;
370 obj[1].alignment = 0;
372 obj[1].flags = EXEC_OBJECT_NEEDS_FENCE;
376 obj[2].handle = handle;
377 obj[2].relocation_count = 2;
378 obj[2].relocs_ptr = (uintptr_t)reloc;
379 obj[2].alignment = 0;
382 obj[2].rsvd1 = obj[2].rsvd2 = 0;
384 exec.buffers_ptr = (uintptr_t)obj;
385 exec.buffer_count = 3;
386 exec.batch_start_offset = 0;
387 exec.batch_len = (b-batch)*sizeof(batch[0]);
388 exec.DR1 = exec.DR4 = 0;
389 exec.num_cliprects = 0;
390 exec.cliprects_ptr = 0;
392 i915_execbuffer2_set_context_id(exec, 0);
395 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
396 while (ret && errno == EBUSY) {
397 drmCommandNone(fd, DRM_I915_GEM_THROTTLE);
398 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
400 igt_assert(ret == 0);
402 gem_close(fd, handle);
408 uint32_t dst, int dst_tiling,
409 uint32_t src, int src_tiling)
412 switch (random() % 3) {
413 case 0: render_copy(fd, dst, dst_tiling, src, src_tiling, 0); break;
414 case 1: render_copy(fd, dst, dst_tiling, src, src_tiling, 1); break;
415 case 2: if (dst_tiling == I915_TILING_Y || src_tiling == I915_TILING_Y)
417 blt_copy(fd, dst, src);
423 create_bo(int fd, uint32_t val, int tiling)
429 handle = gem_create(fd, WIDTH*HEIGHT*4);
430 gem_set_tiling(fd, handle, tiling, WIDTH*4);
432 /* Fill the BO with dwords starting at val */
433 v = gem_mmap(fd, handle, WIDTH*HEIGHT*4, PROT_READ | PROT_WRITE);
435 for (i = 0; i < WIDTH*HEIGHT; i++)
437 munmap(v, WIDTH*HEIGHT*4);
443 check_bo(int fd, uint32_t handle, uint32_t val)
448 v = gem_mmap(fd, handle, WIDTH*HEIGHT*4, PROT_READ);
450 for (i = 0; i < WIDTH*HEIGHT; i++) {
451 igt_assert_f(v[i] == val,
452 "Expected 0x%08x, found 0x%08x "
453 "at offset 0x%08x\n",
457 munmap(v, WIDTH*HEIGHT*4);
460 int main(int argc, char **argv)
462 uint32_t *handle, *tiling, *start_val;
470 igt_require(IS_GEN3(intel_get_drm_devid(fd)));
474 count = atoi(argv[1]);
476 count = 3 * gem_aperture_size(fd) / (1024*1024) / 2;
477 igt_info("Using %d 1MiB buffers\n", count);
479 handle = malloc(sizeof(uint32_t)*count*3);
480 tiling = handle + count;
481 start_val = tiling + count;
483 for (i = 0; i < count; i++) {
484 handle[i] = create_bo(fd, start, tiling[i] = i % 3);
485 start_val[i] = start;
486 start += 1024 * 1024 / 4;
489 igt_info("Verifying initialisation..."); fflush(stdout);
490 for (i = 0; i < count; i++)
491 check_bo(fd, handle[i], start_val[i]);
494 igt_info("Cyclic blits, forward..."); fflush(stdout);
495 for (i = 0; i < count * 32; i++) {
497 int dst = (i + 1) % count;
499 copy(fd, handle[dst], tiling[dst], handle[src], tiling[src]);
500 start_val[dst] = start_val[src];
502 igt_info("verifying..."); fflush(stdout);
503 for (i = 0; i < count; i++)
504 check_bo(fd, handle[i], start_val[i]);
507 igt_info("Cyclic blits, backward..."); fflush(stdout);
508 for (i = 0; i < count * 32; i++) {
509 int src = (i + 1) % count;
512 copy(fd, handle[dst], tiling[dst], handle[src], tiling[src]);
513 start_val[dst] = start_val[src];
515 igt_info("verifying..."); fflush(stdout);
516 for (i = 0; i < count; i++)
517 check_bo(fd, handle[i], start_val[i]);
520 igt_info("Random blits..."); fflush(stdout);
521 for (i = 0; i < count * 32; i++) {
522 int src = random() % count;
523 int dst = random() % count;
526 dst = random() % count;
528 copy(fd, handle[dst], tiling[dst], handle[src], tiling[src]);
529 start_val[dst] = start_val[src];
531 igt_info("verifying..."); fflush(stdout);
532 for (i = 0; i < count; i++)
533 check_bo(fd, handle[i], start_val[i]);