2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Vetter <daniel.vetter@ffwll.ch>
40 #include "intel_bufmgr.h"
41 #include "intel_batchbuffer.h"
42 #include "intel_gpu_tools.h"
45 #define LOCAL_I915_EXEC_VEBOX (4<<0)
46 bool skipped_all = true;
48 static drm_intel_bufmgr *bufmgr;
49 struct intel_batchbuffer *batch;
50 static drm_intel_bo *load_bo, *target_bo, *dummy_bo;
53 /* Testcase: check read/write syncpoints when switching rings
55 * We've had a bug where the syncpoint for the last write was mangled after a
56 * ring switch using semaphores. This resulted in cpu reads returning before the
57 * write actually completed. This test exercises this.
60 #define COLOR 0xffffffff
61 static void run_test(int ring, const char *testname)
68 printf("running subtest %s\n", testname);
70 target_bo = drm_intel_bo_alloc(bufmgr, "target bo", 4096, 4096);
72 fprintf(stderr, "failed to alloc target buffer\n");
76 /* Need to map first so that we can do our own domain mangement with
78 drm_intel_bo_map(target_bo, 0);
79 ptr = target_bo->virtual;
82 /* put some load onto the gpu to keep the light buffers active for long
84 for (i = 0; i < 1000; i++) {
86 OUT_BATCH(XY_SRC_COPY_BLT_CMD |
87 XY_SRC_COPY_BLT_WRITE_ALPHA |
88 XY_SRC_COPY_BLT_WRITE_RGB);
89 OUT_BATCH((3 << 24) | /* 32 bits */
90 (0xcc << 16) | /* copy ROP */
92 OUT_BATCH(0); /* dst x1,y1 */
93 OUT_BATCH((1024 << 16) | 512);
94 OUT_RELOC(load_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
95 OUT_BATCH((0 << 16) | 512); /* src x1, y1 */
97 OUT_RELOC(load_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
102 OUT_BATCH(XY_COLOR_BLT_CMD |
103 XY_COLOR_BLT_WRITE_ALPHA |
104 XY_COLOR_BLT_WRITE_RGB);
105 OUT_BATCH((3 << 24) | /* 32 bits */
108 OUT_BATCH(0); /* dst x1,y1 */
109 OUT_BATCH((1 << 16) | 1);
110 OUT_RELOC(target_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
114 intel_batchbuffer_flush(batch);
116 /* Emit an empty batch so that signalled seqno on the target ring >
117 * signalled seqnoe on the blt ring. This is required to hit the bug. */
122 intel_batchbuffer_flush_on_ring(batch, ring);
124 /* For the ring->ring sync it's important to only emit a read reloc, for
125 * otherwise the obj->last_write_seqno will be updated. */
126 if (ring == I915_EXEC_RENDER) {
128 OUT_BATCH(MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE);
129 OUT_BATCH(0xffffffff); /* compare dword */
130 OUT_RELOC(target_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
135 OUT_BATCH(MI_FLUSH_DW | 1);
136 OUT_BATCH(0); /* reserved */
137 OUT_RELOC(target_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
138 OUT_BATCH(MI_NOOP | (1<<22) | (0xf));
141 intel_batchbuffer_flush_on_ring(batch, ring);
143 gem_set_domain(fd, target_bo->handle, I915_GEM_DOMAIN_GTT, 0);
144 assert(*ptr == COLOR);
145 drm_intel_bo_unmap(target_bo);
147 drm_intel_bo_unreference(target_bo);
150 static int has_ring(int ring)
153 case I915_EXEC_RENDER: /* test only makes sense with separate blitter */
154 return HAS_BLT_RING(intel_get_drm_devid(fd));
156 return HAS_BSD_RING(intel_get_drm_devid(fd));
157 case LOCAL_I915_EXEC_VEBOX:
158 return gem_has_vebox(fd);
164 int main(int argc, char **argv)
166 static const struct {
170 { "blt2render", I915_EXEC_RENDER },
171 { "blt2bsd", I915_EXEC_BSD },
172 { "blt2vebox", LOCAL_I915_EXEC_VEBOX },
176 drmtest_subtest_init(argc, argv);
180 /* Test requires MI_FLUSH_DW and MI_COND_BATCH_BUFFER_END */
181 if (intel_gen(intel_get_drm_devid(fd)) < 6)
184 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
186 fprintf(stderr, "failed to init libdrm\n");
189 /* don't enable buffer reuse!! */
190 //drm_intel_bufmgr_gem_enable_reuse(bufmgr);
192 batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
195 dummy_bo = drm_intel_bo_alloc(bufmgr, "dummy bo", 4096, 4096);
197 fprintf(stderr, "failed to alloc dummy buffer\n");
201 load_bo = drm_intel_bo_alloc(bufmgr, "load bo", 1024*4096, 4096);
203 fprintf(stderr, "failed to alloc load buffer\n");
207 for (i = 0; i < ARRAY_SIZE(tests); i++) {
208 if (has_ring(tests[i].ring) &&
209 drmtest_run_subtest(tests[i].name))
210 run_test(tests[i].ring, tests[i].name);
213 drmtest_fork_signal_helper();
214 for (i = 0; i < ARRAY_SIZE(tests); i++) {
216 snprintf(name, sizeof(name), "%s-interruptible", tests[i].name);
217 if (has_ring(tests[i].ring) && drmtest_run_subtest(name))
218 run_test(tests[i].ring, name);
220 drmtest_stop_signal_helper();
222 drm_intel_bufmgr_destroy(bufmgr);
226 return skipped_all ? 77 : 0;