2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Vetter <daniel.vetter@ffwll.ch>
39 #include "ioctl_wrappers.h"
41 #include "intel_chipset.h"
46 * Testcase: pwrite/pread consistency when touching partial cachelines
48 * Some fancy new pwrite/pread optimizations clflush in-line while
49 * reading/writing. Check whether all required clflushes happen.
51 * Unfortunately really old mesa used unaligned pread/pwrite for s/w fallback
52 * rendering, so we need to check whether this works on tiled buffers, too.
56 static drm_intel_bufmgr *bufmgr;
57 struct intel_batchbuffer *batch;
59 drm_intel_bo *scratch_bo;
60 drm_intel_bo *staging_bo;
61 drm_intel_bo *tiled_staging_bo;
62 unsigned long scratch_pitch;
63 #define BO_SIZE (32*4096)
65 uint64_t mappable_gtt_limit;
69 copy_bo(drm_intel_bo *src, int src_tiled,
70 drm_intel_bo *dst, int dst_tiled)
72 unsigned long dst_pitch = scratch_pitch;
73 unsigned long src_pitch = scratch_pitch;
74 uint32_t cmd_bits = 0;
76 /* dst is tiled ... */
77 if (intel_gen(devid) >= 4 && dst_tiled) {
79 cmd_bits |= XY_SRC_COPY_BLT_DST_TILED;
82 if (intel_gen(devid) >= 4 && dst_tiled) {
84 cmd_bits |= XY_SRC_COPY_BLT_SRC_TILED;
87 BLIT_COPY_BATCH_START(devid, cmd_bits);
88 OUT_BATCH((3 << 24) | /* 32 bits */
89 (0xcc << 16) | /* copy ROP */
91 OUT_BATCH(0 << 16 | 0);
92 OUT_BATCH(BO_SIZE/scratch_pitch << 16 | 1024);
93 OUT_RELOC_FENCED(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
94 BLIT_RELOC_UDW(devid);
95 OUT_BATCH(0 << 16 | 0);
97 OUT_RELOC_FENCED(src, I915_GEM_DOMAIN_RENDER, 0, 0);
98 BLIT_RELOC_UDW(devid);
101 intel_batchbuffer_flush(batch);
105 blt_bo_fill(drm_intel_bo *tmp_bo, drm_intel_bo *bo, int val)
110 drm_intel_gem_bo_map_gtt(tmp_bo);
111 gtt_ptr = tmp_bo->virtual;
113 for (i = 0; i < BO_SIZE; i++)
116 drm_intel_gem_bo_unmap_gtt(tmp_bo);
118 if (bo->offset < mappable_gtt_limit &&
119 (IS_G33(devid) || intel_gen(devid) >= 4))
120 igt_trash_aperture();
122 copy_bo(tmp_bo, 0, bo, 1);
125 #define MAX_BLT_SIZE 128
127 uint8_t tmp[BO_SIZE];
128 uint8_t compare_tmp[BO_SIZE];
130 static void test_partial_reads(void)
134 printf("checking partial reads\n");
135 for (i = 0; i < ROUNDS; i++) {
139 blt_bo_fill(staging_bo, scratch_bo, i);
141 start = random() % BO_SIZE;
142 len = random() % (BO_SIZE-start) + 1;
144 drm_intel_bo_get_subdata(scratch_bo, start, len, tmp);
145 for (j = 0; j < len; j++) {
146 igt_assert_f(tmp[j] == val,
147 "mismatch at %i, got: %i, expected: %i\n",
148 start + j, tmp[j], val);
151 igt_progress("partial reads test: ", i, ROUNDS);
155 static void test_partial_writes(void)
159 printf("checking partial writes\n");
160 for (i = 0; i < ROUNDS; i++) {
164 blt_bo_fill(staging_bo, scratch_bo, i);
166 start = random() % BO_SIZE;
167 len = random() % (BO_SIZE-start) + 1;
169 memset(tmp, i + 63, BO_SIZE);
171 drm_intel_bo_subdata(scratch_bo, start, len, tmp);
173 copy_bo(scratch_bo, 1, tiled_staging_bo, 1);
174 drm_intel_bo_get_subdata(tiled_staging_bo, 0, BO_SIZE,
177 for (j = 0; j < start; j++) {
178 igt_assert_f(compare_tmp[j] == val,
179 "mismatch at %i, got: %i, expected: %i\n",
182 for (; j < start + len; j++) {
183 igt_assert_f(compare_tmp[j] == tmp[0],
184 "mismatch at %i, got: %i, expected: %i\n",
187 for (; j < BO_SIZE; j++) {
188 igt_assert_f(compare_tmp[j] == val,
189 "mismatch at %i, got: %i, expected: %i\n",
192 drm_intel_gem_bo_unmap_gtt(staging_bo);
194 igt_progress("partial writes test: ", i, ROUNDS);
198 static void test_partial_read_writes(void)
202 printf("checking partial writes after partial reads\n");
203 for (i = 0; i < ROUNDS; i++) {
207 blt_bo_fill(staging_bo, scratch_bo, i);
210 start = random() % BO_SIZE;
211 len = random() % (BO_SIZE-start) + 1;
213 drm_intel_bo_get_subdata(scratch_bo, start, len, tmp);
214 for (j = 0; j < len; j++) {
215 igt_assert_f(tmp[j] == val,
216 "mismatch in read at %i, got: %i, expected: %i\n",
217 start + j, tmp[j], val);
220 /* Change contents through gtt to make the pread cachelines
222 val = (i + 17) % 256;
223 blt_bo_fill(staging_bo, scratch_bo, val);
226 start = random() % BO_SIZE;
227 len = random() % (BO_SIZE-start) + 1;
229 memset(tmp, i + 63, BO_SIZE);
231 drm_intel_bo_subdata(scratch_bo, start, len, tmp);
233 copy_bo(scratch_bo, 1, tiled_staging_bo, 1);
234 drm_intel_bo_get_subdata(tiled_staging_bo, 0, BO_SIZE,
237 for (j = 0; j < start; j++) {
238 igt_assert_f(compare_tmp[j] == val,
239 "mismatch at %i, got: %i, expected: %i\n",
242 for (; j < start + len; j++) {
243 igt_assert_f(compare_tmp[j] == tmp[0],
244 "mismatch at %i, got: %i, expected: %i\n",
247 for (; j < BO_SIZE; j++) {
248 igt_assert_f(compare_tmp[j] == val,
249 "mismatch at %i, got: %i, expected: %i\n",
252 drm_intel_gem_bo_unmap_gtt(staging_bo);
254 igt_progress("partial read/writes test: ", i, ROUNDS);
260 uint32_t tiling_mode = I915_TILING_X;
262 igt_skip_on_simulation();
269 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
270 //drm_intel_bufmgr_gem_enable_reuse(bufmgr);
271 devid = intel_get_drm_devid(fd);
272 batch = intel_batchbuffer_alloc(bufmgr, devid);
274 /* overallocate the buffers we're actually using because */
275 scratch_bo = drm_intel_bo_alloc_tiled(bufmgr, "scratch bo", 1024,
277 &tiling_mode, &scratch_pitch, 0);
278 igt_assert(tiling_mode == I915_TILING_X);
279 igt_assert(scratch_pitch == 4096);
280 staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
281 tiled_staging_bo = drm_intel_bo_alloc_tiled(bufmgr, "scratch bo", 1024,
286 igt_init_aperture_trashers(bufmgr);
287 mappable_gtt_limit = gem_mappable_aperture_size();
291 test_partial_reads();
293 igt_subtest("writes")
294 test_partial_writes();
296 igt_subtest("writes-after-reads")
297 test_partial_read_writes();
300 igt_cleanup_aperture_trashers();
301 drm_intel_bufmgr_destroy(bufmgr);