2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Vetter <daniel.vetter@ffwll.ch>
40 #include "intel_bufmgr.h"
41 #include "intel_batchbuffer.h"
42 #include "intel_gpu_tools.h"
45 * Testcase: pwrite/pread consistency when touching partial cachelines
47 * Some fancy new pwrite/pread optimizations clflush in-line while
48 * reading/writing. Check whether all required clflushes happen.
50 * Unfortunately really old mesa used unaligned pread/pwrite for s/w fallback
51 * rendering, so we need to check whether this works on tiled buffers, too.
55 static drm_intel_bufmgr *bufmgr;
56 struct intel_batchbuffer *batch;
58 drm_intel_bo *scratch_bo;
59 drm_intel_bo *staging_bo;
60 drm_intel_bo *tiled_staging_bo;
61 unsigned long scratch_pitch;
62 #define BO_SIZE (32*4096)
64 uint64_t mappable_gtt_limit;
68 copy_bo(drm_intel_bo *src, int src_tiled,
69 drm_intel_bo *dst, int dst_tiled)
71 unsigned long dst_pitch = scratch_pitch;
72 unsigned long src_pitch = scratch_pitch;
73 uint32_t cmd_bits = 0;
75 /* dst is tiled ... */
76 if (intel_gen(devid) >= 4 && dst_tiled) {
78 cmd_bits |= XY_SRC_COPY_BLT_DST_TILED;
81 if (intel_gen(devid) >= 4 && dst_tiled) {
83 cmd_bits |= XY_SRC_COPY_BLT_SRC_TILED;
87 OUT_BATCH(XY_SRC_COPY_BLT_CMD |
88 XY_SRC_COPY_BLT_WRITE_ALPHA |
89 XY_SRC_COPY_BLT_WRITE_RGB |
91 OUT_BATCH((3 << 24) | /* 32 bits */
92 (0xcc << 16) | /* copy ROP */
94 OUT_BATCH(0 << 16 | 0);
95 OUT_BATCH(BO_SIZE/scratch_pitch << 16 | 1024);
96 OUT_RELOC_FENCED(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
97 OUT_BATCH(0 << 16 | 0);
99 OUT_RELOC_FENCED(src, I915_GEM_DOMAIN_RENDER, 0, 0);
102 intel_batchbuffer_flush(batch);
106 blt_bo_fill(drm_intel_bo *tmp_bo, drm_intel_bo *bo, int val)
111 drm_intel_gem_bo_map_gtt(tmp_bo);
112 gtt_ptr = tmp_bo->virtual;
114 for (i = 0; i < BO_SIZE; i++)
117 drm_intel_gem_bo_unmap_gtt(tmp_bo);
119 if (bo->offset < mappable_gtt_limit &&
120 (IS_G33(devid) || intel_gen(devid) >= 4))
121 drmtest_trash_aperture();
123 copy_bo(tmp_bo, 0, bo, 1);
126 #define MAX_BLT_SIZE 128
128 uint8_t tmp[BO_SIZE];
129 uint8_t compare_tmp[BO_SIZE];
131 static void test_partial_reads(void)
135 printf("checking partial reads\n");
136 for (i = 0; i < ROUNDS; i++) {
140 blt_bo_fill(staging_bo, scratch_bo, i);
142 start = random() % BO_SIZE;
143 len = random() % (BO_SIZE-start) + 1;
145 drm_intel_bo_get_subdata(scratch_bo, start, len, tmp);
146 for (j = 0; j < len; j++) {
148 printf("mismatch at %i, got: %i, expected: %i\n",
149 start + j, tmp[j], val);
154 drmtest_progress("partial reads test: ", i, ROUNDS);
158 static void test_partial_writes(void)
162 printf("checking partial writes\n");
163 for (i = 0; i < ROUNDS; i++) {
167 blt_bo_fill(staging_bo, scratch_bo, i);
169 start = random() % BO_SIZE;
170 len = random() % (BO_SIZE-start) + 1;
172 memset(tmp, i + 63, BO_SIZE);
174 drm_intel_bo_subdata(scratch_bo, start, len, tmp);
176 copy_bo(scratch_bo, 1, tiled_staging_bo, 1);
177 drm_intel_bo_get_subdata(tiled_staging_bo, 0, BO_SIZE,
180 for (j = 0; j < start; j++) {
181 if (compare_tmp[j] != val) {
182 printf("amismatch at %i, got: %i, expected: %i\n",
187 for (; j < start + len; j++) {
188 if (compare_tmp[j] != tmp[0]) {
189 printf("bmismatch at %i, got: %i, expected: %i\n",
194 for (; j < BO_SIZE; j++) {
195 if (compare_tmp[j] != val) {
196 printf("cmismatch at %i, got: %i, expected: %i\n",
201 drm_intel_gem_bo_unmap_gtt(staging_bo);
203 drmtest_progress("partial writes test: ", i, ROUNDS);
207 static void test_partial_read_writes(void)
211 printf("checking partial writes after partial reads\n");
212 for (i = 0; i < ROUNDS; i++) {
216 blt_bo_fill(staging_bo, scratch_bo, i);
219 start = random() % BO_SIZE;
220 len = random() % (BO_SIZE-start) + 1;
222 drm_intel_bo_get_subdata(scratch_bo, start, len, tmp);
223 for (j = 0; j < len; j++) {
225 printf("mismatch in read at %i, got: %i, expected: %i\n",
226 start + j, tmp[j], val);
231 /* Change contents through gtt to make the pread cachelines
233 val = (i + 17) % 256;
234 blt_bo_fill(staging_bo, scratch_bo, val);
237 start = random() % BO_SIZE;
238 len = random() % (BO_SIZE-start) + 1;
240 memset(tmp, i + 63, BO_SIZE);
242 drm_intel_bo_subdata(scratch_bo, start, len, tmp);
244 copy_bo(scratch_bo, 1, tiled_staging_bo, 1);
245 drm_intel_bo_get_subdata(tiled_staging_bo, 0, BO_SIZE,
248 for (j = 0; j < start; j++) {
249 if (compare_tmp[j] != val) {
250 printf("mismatch at %i, got: %i, expected: %i\n",
255 for (; j < start + len; j++) {
256 if (compare_tmp[j] != tmp[0]) {
257 printf("mismatch at %i, got: %i, expected: %i\n",
262 for (; j < BO_SIZE; j++) {
263 if (compare_tmp[j] != val) {
264 printf("mismatch at %i, got: %i, expected: %i\n",
269 drm_intel_gem_bo_unmap_gtt(staging_bo);
271 drmtest_progress("partial read/writes test: ", i, ROUNDS);
275 int main(int argc, char **argv)
277 uint32_t tiling_mode = I915_TILING_X;
279 drmtest_subtest_init(argc, argv);
285 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
286 //drm_intel_bufmgr_gem_enable_reuse(bufmgr);
287 devid = intel_get_drm_devid(fd);
288 batch = intel_batchbuffer_alloc(bufmgr, devid);
290 /* overallocate the buffers we're actually using because */
291 scratch_bo = drm_intel_bo_alloc_tiled(bufmgr, "scratch bo", 1024,
293 &tiling_mode, &scratch_pitch, 0);
294 assert(tiling_mode == I915_TILING_X);
295 assert(scratch_pitch == 4096);
296 staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
297 tiled_staging_bo = drm_intel_bo_alloc_tiled(bufmgr, "scratch bo", 1024,
302 drmtest_init_aperture_trashers(bufmgr);
303 mappable_gtt_limit = gem_mappable_aperture_size();
305 if (drmtest_run_subtest("reads"))
306 test_partial_reads();
308 if (drmtest_run_subtest("writes"))
309 test_partial_writes();
311 if (drmtest_run_subtest("writes-after-reads"))
312 test_partial_read_writes();
314 drmtest_cleanup_aperture_trashers();
315 drm_intel_bufmgr_destroy(bufmgr);