tests/gem_tiled_partial_pwrite_pread.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Daniel Vetter <daniel.vetter@ffwll.ch>
  25  *
  26  */
  27
  28 #include <stdlib.h>
  29 #include <stdio.h>
  30 #include <string.h>
  31 #include <assert.h>
  32 #include <fcntl.h>
  33 #include <inttypes.h>
  34 #include <errno.h>
  35 #include <sys/stat.h>
  36 #include <sys/time.h>
  37 #include "drm.h"
  38 #include "i915_drm.h"
  39 #include "drmtest.h"
  40 #include "intel_bufmgr.h"
  41 #include "intel_batchbuffer.h"
  42 #include "intel_gpu_tools.h"
  43
  44 /*
  45  * Testcase: pwrite/pread consistency when touching partial cachelines
  46  *
  47  * Some fancy new pwrite/pread optimizations clflush in-line while
  48  * reading/writing. Check whether all required clflushes happen.
  49  *
  50  * Unfortunately really old mesa used unaligned pread/pwrite for s/w fallback
  51  * rendering, so we need to check whether this works on tiled buffers, too.
  52  *
  53  */
  54
  55 static drm_intel_bufmgr *bufmgr;
  56 struct intel_batchbuffer *batch;
  57
  58 drm_intel_bo *scratch_bo;
  59 drm_intel_bo *staging_bo;
  60 drm_intel_bo *tiled_staging_bo;
  61 unsigned long scratch_pitch;
  62 #define BO_SIZE (32*4096)
  63 uint32_t devid;
  64 uint64_t mappable_gtt_limit;
  65 int fd;
  66
  67 static void
  68 copy_bo(drm_intel_bo *src, int src_tiled,
  69         drm_intel_bo *dst, int dst_tiled)
  70 {
  71         unsigned long dst_pitch = scratch_pitch;
  72         unsigned long src_pitch = scratch_pitch;
  73         uint32_t cmd_bits = 0;
  74
  75         /* dst is tiled ... */
  76         if (intel_gen(devid) >= 4 && dst_tiled) {
  77                 dst_pitch /= 4;
  78                 cmd_bits |= XY_SRC_COPY_BLT_DST_TILED;
  79         }
  80
  81         if (intel_gen(devid) >= 4 && dst_tiled) {
  82                 src_pitch /= 4;
  83                 cmd_bits |= XY_SRC_COPY_BLT_SRC_TILED;
  84         }
  85
  86         BEGIN_BATCH(8);
  87         OUT_BATCH(XY_SRC_COPY_BLT_CMD |
  88                   XY_SRC_COPY_BLT_WRITE_ALPHA |
  89                   XY_SRC_COPY_BLT_WRITE_RGB |
  90                   cmd_bits);
  91         OUT_BATCH((3 << 24) | /* 32 bits */
  92                   (0xcc << 16) | /* copy ROP */
  93                   dst_pitch);
  94         OUT_BATCH(0 << 16 | 0);
  95         OUT_BATCH(BO_SIZE/scratch_pitch << 16 | 1024);
  96         OUT_RELOC_FENCED(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
  97         OUT_BATCH(0 << 16 | 0);
  98         OUT_BATCH(src_pitch);
  99         OUT_RELOC_FENCED(src, I915_GEM_DOMAIN_RENDER, 0, 0);
 100         ADVANCE_BATCH();
 101
 102         intel_batchbuffer_flush(batch);
 103 }
 104
 105 static void
 106 blt_bo_fill(drm_intel_bo *tmp_bo, drm_intel_bo *bo, int val)
 107 {
 108         uint8_t *gtt_ptr;
 109         int i;
 110
 111         drm_intel_gem_bo_map_gtt(tmp_bo);
 112         gtt_ptr = tmp_bo->virtual;
 113
 114         for (i = 0; i < BO_SIZE; i++)
 115                 gtt_ptr[i] = val;
 116
 117         drm_intel_gem_bo_unmap_gtt(tmp_bo);
 118
 119         if (bo->offset < mappable_gtt_limit &&
 120             (IS_G33(devid) || intel_gen(devid) >= 4))
 121                 drmtest_trash_aperture();
 122
 123         copy_bo(tmp_bo, 0, bo, 1);
 124 }
 125
 126 #define MAX_BLT_SIZE 128
 127 #define ROUNDS 200
 128 int main(int argc, char **argv)
 129 {
 130         int i, j;
 131         uint8_t tmp[BO_SIZE];
 132         uint8_t compare_tmp[BO_SIZE];
 133         uint32_t tiling_mode = I915_TILING_X;
 134
 135         srandom(0xdeadbeef);
 136
 137         fd = drm_open_any();
 138
 139         bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
 140         //drm_intel_bufmgr_gem_enable_reuse(bufmgr);
 141         devid = intel_get_drm_devid(fd);
 142         batch = intel_batchbuffer_alloc(bufmgr, devid);
 143
 144         /* overallocate the buffers we're actually using because */
 145         scratch_bo = drm_intel_bo_alloc_tiled(bufmgr, "scratch bo", 1024,
 146                                               BO_SIZE/4096, 4,
 147                                               &tiling_mode, &scratch_pitch, 0);
 148         assert(tiling_mode == I915_TILING_X);
 149         assert(scratch_pitch == 4096);
 150         staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
 151         tiled_staging_bo = drm_intel_bo_alloc_tiled(bufmgr, "scratch bo", 1024,
 152                                                     BO_SIZE/4096, 4,
 153                                                     &tiling_mode,
 154                                                     &scratch_pitch, 0);
 155
 156         drmtest_init_aperture_trashers(bufmgr);
 157         mappable_gtt_limit = gem_mappable_aperture_size();
 158
 159         printf("checking partial reads\n");
 160         for (i = 0; i < ROUNDS; i++) {
 161                 int start, len;
 162                 int val = i % 256;
 163
 164                 blt_bo_fill(staging_bo, scratch_bo, i);
 165
 166                 start = random() % BO_SIZE;
 167                 len = random() % (BO_SIZE-start) + 1;
 168
 169                 drm_intel_bo_get_subdata(scratch_bo, start, len, tmp);
 170                 for (j = 0; j < len; j++) {
 171                         if (tmp[j] != val) {
 172                                 printf("mismatch at %i, got: %i, expected: %i\n",
 173                                        start + j, tmp[j], val);
 174                                 exit(1);
 175                         }
 176                 }
 177
 178                 drmtest_progress("partial reads test: ", i, ROUNDS);
 179         }
 180
 181         printf("checking partial writes\n");
 182         for (i = 0; i < ROUNDS; i++) {
 183                 int start, len;
 184                 int val = i % 256;
 185
 186                 blt_bo_fill(staging_bo, scratch_bo, i);
 187
 188                 start = random() % BO_SIZE;
 189                 len = random() % (BO_SIZE-start) + 1;
 190
 191                 memset(tmp, i + 63, BO_SIZE);
 192
 193                 drm_intel_bo_subdata(scratch_bo, start, len, tmp);
 194
 195                 copy_bo(scratch_bo, 1, tiled_staging_bo, 1);
 196                 drm_intel_bo_get_subdata(tiled_staging_bo, 0, BO_SIZE,
 197                                          compare_tmp);
 198
 199                 for (j = 0; j < start; j++) {
 200                         if (compare_tmp[j] != val) {
 201                                 printf("amismatch at %i, got: %i, expected: %i\n",
 202                                        j, tmp[j], val);
 203                                 exit(1);
 204                         }
 205                 }
 206                 for (; j < start + len; j++) {
 207                         if (compare_tmp[j] != tmp[0]) {
 208                                 printf("bmismatch at %i, got: %i, expected: %i\n",
 209                                        j, tmp[j], i);
 210                                 exit(1);
 211                         }
 212                 }
 213                 for (; j < BO_SIZE; j++) {
 214                         if (compare_tmp[j] != val) {
 215                                 printf("cmismatch at %i, got: %i, expected: %i\n",
 216                                        j, tmp[j], val);
 217                                 exit(1);
 218                         }
 219                 }
 220                 drm_intel_gem_bo_unmap_gtt(staging_bo);
 221
 222                 drmtest_progress("partial writes test: ", i, ROUNDS);
 223         }
 224
 225         printf("checking partial writes after partial reads\n");
 226         for (i = 0; i < ROUNDS; i++) {
 227                 int start, len;
 228                 int val = i % 256;
 229
 230                 blt_bo_fill(staging_bo, scratch_bo, i);
 231
 232                 /* partial read */
 233                 start = random() % BO_SIZE;
 234                 len = random() % (BO_SIZE-start) + 1;
 235
 236                 drm_intel_bo_get_subdata(scratch_bo, start, len, tmp);
 237                 for (j = 0; j < len; j++) {
 238                         if (tmp[j] != val) {
 239                                 printf("mismatch in read at %i, got: %i, expected: %i\n",
 240                                        start + j, tmp[j], val);
 241                                 exit(1);
 242                         }
 243                 }
 244
 245                 /* Change contents through gtt to make the pread cachelines
 246                  * stale. */
 247                 val = (i + 17) % 256;
 248                 blt_bo_fill(staging_bo, scratch_bo, val);
 249
 250                 /* partial write */
 251                 start = random() % BO_SIZE;
 252                 len = random() % (BO_SIZE-start) + 1;
 253
 254                 memset(tmp, i + 63, BO_SIZE);
 255
 256                 drm_intel_bo_subdata(scratch_bo, start, len, tmp);
 257
 258                 copy_bo(scratch_bo, 1, tiled_staging_bo, 1);
 259                 drm_intel_bo_get_subdata(tiled_staging_bo, 0, BO_SIZE,
 260                                          compare_tmp);
 261
 262                 for (j = 0; j < start; j++) {
 263                         if (compare_tmp[j] != val) {
 264                                 printf("mismatch at %i, got: %i, expected: %i\n",
 265                                        j, tmp[j], val);
 266                                 exit(1);
 267                         }
 268                 }
 269                 for (; j < start + len; j++) {
 270                         if (compare_tmp[j] != tmp[0]) {
 271                                 printf("mismatch at %i, got: %i, expected: %i\n",
 272                                        j, tmp[j], tmp[0]);
 273                                 exit(1);
 274                         }
 275                 }
 276                 for (; j < BO_SIZE; j++) {
 277                         if (compare_tmp[j] != val) {
 278                                 printf("mismatch at %i, got: %i, expected: %i\n",
 279                                        j, tmp[j], val);
 280                                 exit(1);
 281                         }
 282                 }
 283                 drm_intel_gem_bo_unmap_gtt(staging_bo);
 284
 285                 drmtest_progress("partial read/writes test: ", i, ROUNDS);
 286         }
 287
 288         drmtest_cleanup_aperture_trashers();
 289         drm_intel_bufmgr_destroy(bufmgr);
 290
 291         close(fd);
 292
 293         return 0;
 294 }