2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Vetter <daniel.vetter@ffwll.ch>
39 #include "ioctl_wrappers.h"
41 #include "intel_chipset.h"
46 * Testcase: pwrite/pread consistency when touching partial cachelines
48 * Some fancy new pwrite/pread optimizations clflush in-line while
49 * reading/writing. Check whether all required clflushes happen.
51 * Unfortunately really old mesa used unaligned pread/pwrite for s/w fallback
52 * rendering, so we need to check whether this works on tiled buffers, too.
56 static drm_intel_bufmgr *bufmgr;
57 struct intel_batchbuffer *batch;
59 drm_intel_bo *scratch_bo;
60 drm_intel_bo *staging_bo;
61 drm_intel_bo *tiled_staging_bo;
62 unsigned long scratch_pitch;
63 #define BO_SIZE (32*4096)
65 uint64_t mappable_gtt_limit;
69 copy_bo(drm_intel_bo *src, int src_tiled,
70 drm_intel_bo *dst, int dst_tiled)
72 unsigned long dst_pitch = scratch_pitch;
73 unsigned long src_pitch = scratch_pitch;
74 uint32_t cmd_bits = 0;
76 /* dst is tiled ... */
77 if (intel_gen(devid) >= 4 && dst_tiled) {
79 cmd_bits |= XY_SRC_COPY_BLT_DST_TILED;
82 if (intel_gen(devid) >= 4 && dst_tiled) {
84 cmd_bits |= XY_SRC_COPY_BLT_SRC_TILED;
87 BLIT_COPY_BATCH_START(devid, cmd_bits);
88 OUT_BATCH((3 << 24) | /* 32 bits */
89 (0xcc << 16) | /* copy ROP */
91 OUT_BATCH(0 << 16 | 0);
92 OUT_BATCH(BO_SIZE/scratch_pitch << 16 | 1024);
93 OUT_RELOC_FENCED(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
94 BLIT_RELOC_UDW(devid);
95 OUT_BATCH(0 << 16 | 0);
97 OUT_RELOC_FENCED(src, I915_GEM_DOMAIN_RENDER, 0, 0);
98 BLIT_RELOC_UDW(devid);
101 intel_batchbuffer_flush(batch);
105 blt_bo_fill(drm_intel_bo *tmp_bo, drm_intel_bo *bo, int val)
110 drm_intel_gem_bo_map_gtt(tmp_bo);
111 gtt_ptr = tmp_bo->virtual;
113 for (i = 0; i < BO_SIZE; i++)
116 drm_intel_gem_bo_unmap_gtt(tmp_bo);
118 if (bo->offset < mappable_gtt_limit &&
119 (IS_G33(devid) || intel_gen(devid) >= 4))
120 igt_trash_aperture();
122 copy_bo(tmp_bo, 0, bo, 1);
125 #define MAX_BLT_SIZE 128
127 uint8_t tmp[BO_SIZE];
128 uint8_t compare_tmp[BO_SIZE];
130 static void test_partial_reads(void)
134 for (i = 0; i < ROUNDS; i++) {
138 blt_bo_fill(staging_bo, scratch_bo, i);
140 start = random() % BO_SIZE;
141 len = random() % (BO_SIZE-start) + 1;
143 drm_intel_bo_get_subdata(scratch_bo, start, len, tmp);
144 for (j = 0; j < len; j++) {
145 igt_assert_f(tmp[j] == val,
146 "mismatch at %i, got: %i, expected: %i\n",
147 start + j, tmp[j], val);
150 igt_progress("partial reads test: ", i, ROUNDS);
154 static void test_partial_writes(void)
158 for (i = 0; i < ROUNDS; i++) {
162 blt_bo_fill(staging_bo, scratch_bo, i);
164 start = random() % BO_SIZE;
165 len = random() % (BO_SIZE-start) + 1;
167 memset(tmp, i + 63, BO_SIZE);
169 drm_intel_bo_subdata(scratch_bo, start, len, tmp);
171 copy_bo(scratch_bo, 1, tiled_staging_bo, 1);
172 drm_intel_bo_get_subdata(tiled_staging_bo, 0, BO_SIZE,
175 for (j = 0; j < start; j++) {
176 igt_assert_f(compare_tmp[j] == val,
177 "mismatch at %i, got: %i, expected: %i\n",
180 for (; j < start + len; j++) {
181 igt_assert_f(compare_tmp[j] == tmp[0],
182 "mismatch at %i, got: %i, expected: %i\n",
185 for (; j < BO_SIZE; j++) {
186 igt_assert_f(compare_tmp[j] == val,
187 "mismatch at %i, got: %i, expected: %i\n",
190 drm_intel_gem_bo_unmap_gtt(staging_bo);
192 igt_progress("partial writes test: ", i, ROUNDS);
196 static void test_partial_read_writes(void)
200 for (i = 0; i < ROUNDS; i++) {
204 blt_bo_fill(staging_bo, scratch_bo, i);
207 start = random() % BO_SIZE;
208 len = random() % (BO_SIZE-start) + 1;
210 drm_intel_bo_get_subdata(scratch_bo, start, len, tmp);
211 for (j = 0; j < len; j++) {
212 igt_assert_f(tmp[j] == val,
213 "mismatch in read at %i, got: %i, expected: %i\n",
214 start + j, tmp[j], val);
217 /* Change contents through gtt to make the pread cachelines
219 val = (i + 17) % 256;
220 blt_bo_fill(staging_bo, scratch_bo, val);
223 start = random() % BO_SIZE;
224 len = random() % (BO_SIZE-start) + 1;
226 memset(tmp, i + 63, BO_SIZE);
228 drm_intel_bo_subdata(scratch_bo, start, len, tmp);
230 copy_bo(scratch_bo, 1, tiled_staging_bo, 1);
231 drm_intel_bo_get_subdata(tiled_staging_bo, 0, BO_SIZE,
234 for (j = 0; j < start; j++) {
235 igt_assert_f(compare_tmp[j] == val,
236 "mismatch at %i, got: %i, expected: %i\n",
239 for (; j < start + len; j++) {
240 igt_assert_f(compare_tmp[j] == tmp[0],
241 "mismatch at %i, got: %i, expected: %i\n",
244 for (; j < BO_SIZE; j++) {
245 igt_assert_f(compare_tmp[j] == val,
246 "mismatch at %i, got: %i, expected: %i\n",
249 drm_intel_gem_bo_unmap_gtt(staging_bo);
251 igt_progress("partial read/writes test: ", i, ROUNDS);
257 uint32_t tiling_mode = I915_TILING_X;
259 igt_skip_on_simulation();
266 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
267 //drm_intel_bufmgr_gem_enable_reuse(bufmgr);
268 devid = intel_get_drm_devid(fd);
269 batch = intel_batchbuffer_alloc(bufmgr, devid);
271 /* overallocate the buffers we're actually using because */
272 scratch_bo = drm_intel_bo_alloc_tiled(bufmgr, "scratch bo", 1024,
274 &tiling_mode, &scratch_pitch, 0);
275 igt_assert(tiling_mode == I915_TILING_X);
276 igt_assert(scratch_pitch == 4096);
277 staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
278 tiled_staging_bo = drm_intel_bo_alloc_tiled(bufmgr, "scratch bo", 1024,
283 igt_init_aperture_trashers(bufmgr);
284 mappable_gtt_limit = gem_mappable_aperture_size();
288 test_partial_reads();
290 igt_subtest("writes")
291 test_partial_writes();
293 igt_subtest("writes-after-reads")
294 test_partial_read_writes();
297 igt_cleanup_aperture_trashers();
298 drm_intel_bufmgr_destroy(bufmgr);