2 * Copyright © 2009 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
28 /** @file gem_tiled_blits.c
30 * This is a test of doing many tiled blits, with a working set
31 * larger than the aperture size.
33 * The goal is to catch a couple types of failure;
34 * - Fence management problems on pre-965.
35 * - A17 or L-shaped memory tiling workaround problems in acceleration.
37 * The model is to fill a collection of 1MB objects in a way that can't trip
38 * over A6 swizzling -- upload data to a non-tiled object, blit to the tiled
39 * object. Then, copy the 1MB objects randomly between each other for a while.
40 * Finally, download their data through linear objects again and see what
55 #include "ioctl_wrappers.h"
57 #include "intel_chipset.h"
61 static drm_intel_bufmgr *bufmgr;
62 struct intel_batchbuffer *batch;
63 static int width = 512, height = 512;
66 create_bo(uint32_t start_val)
68 drm_intel_bo *bo, *linear_bo;
70 uint32_t tiling = I915_TILING_X;
73 bo = drm_intel_bo_alloc(bufmgr, "tiled bo", 1024 * 1024, 4096);
74 do_or_die(drm_intel_bo_set_tiling(bo, &tiling, width * 4));
75 igt_assert(tiling == I915_TILING_X);
77 linear_bo = drm_intel_bo_alloc(bufmgr, "linear src", 1024 * 1024, 4096);
79 /* Fill the BO with dwords starting at start_val */
80 do_or_die(drm_intel_bo_map(linear_bo, 1));
81 linear = linear_bo->virtual;
82 for (i = 0; i < 1024 * 1024 / 4; i++)
83 linear[i] = start_val++;
84 drm_intel_bo_unmap(linear_bo);
86 intel_copy_bo (batch, bo, linear_bo, width*height*4);
88 drm_intel_bo_unreference(linear_bo);
94 check_bo(drm_intel_bo *bo, uint32_t start_val)
96 drm_intel_bo *linear_bo;
100 linear_bo = drm_intel_bo_alloc(bufmgr, "linear dst", 1024 * 1024, 4096);
102 intel_copy_bo(batch, linear_bo, bo, width*height*4);
104 do_or_die(drm_intel_bo_map(linear_bo, 0));
105 linear = linear_bo->virtual;
107 for (i = 0; i < 1024 * 1024 / 4; i++) {
108 igt_assert_f(linear[i] == start_val,
109 "Expected 0x%08x, found 0x%08x "
110 "at offset 0x%08x\n",
111 start_val, linear[i], i * 4);
114 drm_intel_bo_unmap(linear_bo);
116 drm_intel_bo_unreference(linear_bo);
119 static void run_test(int count)
122 uint32_t *bo_start_val;
126 bo = malloc(sizeof(drm_intel_bo *)*count);
127 bo_start_val = malloc(sizeof(uint32_t)*count);
129 for (i = 0; i < count; i++) {
130 bo[i] = create_bo(start);
131 bo_start_val[i] = start;
132 start += 1024 * 1024 / 4;
134 igt_info("Verifying initialisation...\n");
135 for (i = 0; i < count; i++)
136 check_bo(bo[i], bo_start_val[i]);
138 igt_info("Cyclic blits, forward...\n");
139 for (i = 0; i < count * 4; i++) {
141 int dst = (i+1) % count;
146 intel_copy_bo(batch, bo[dst], bo[src], width*height*4);
147 bo_start_val[dst] = bo_start_val[src];
149 for (i = 0; i < count; i++)
150 check_bo(bo[i], bo_start_val[i]);
152 if (igt_run_in_simulation()) {
153 for (i = 0; i < count; i++)
154 drm_intel_bo_unreference(bo[i]);
160 igt_info("Cyclic blits, backward...\n");
161 for (i = 0; i < count * 4; i++) {
162 int src = (i+1) % count;
168 intel_copy_bo(batch, bo[dst], bo[src], width*height*4);
169 bo_start_val[dst] = bo_start_val[src];
171 for (i = 0; i < count; i++)
172 check_bo(bo[i], bo_start_val[i]);
174 igt_info("Random blits...\n");
175 for (i = 0; i < count * 4; i++) {
176 int src = random() % count;
177 int dst = random() % count;
182 intel_copy_bo(batch, bo[dst], bo[src], width*height*4);
183 bo_start_val[dst] = bo_start_val[src];
185 for (i = 0; i < count; i++) {
186 check_bo(bo[i], bo_start_val[i]);
187 drm_intel_bo_unreference(bo[i]);
196 int main(int argc, char **argv)
200 igt_subtest_init(argc, argv);
205 if (igt_run_in_simulation())
208 count = atoi(argv[1]);
210 count = 3 * gem_aperture_size(fd) / (1024*1024) / 2;
211 count += (count & 1) == 0;
212 } else if (count < 2) {
213 fprintf(stderr, "count must be >= 2\n");
217 if (count > intel_get_total_ram_mb() * 9 / 10) {
218 count = intel_get_total_ram_mb() * 9 / 10;
219 igt_info("not enough RAM to run test, reducing buffer count\n");
222 igt_info("Using %d 1MiB buffers\n", count);
224 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
225 drm_intel_bufmgr_gem_enable_reuse(bufmgr);
226 drm_intel_bufmgr_gem_set_vma_cache_size(bufmgr, 32);
227 batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
230 igt_subtest("normal")
233 igt_subtest("interruptible") {
234 igt_fork_signal_helper();
236 igt_stop_signal_helper();
240 intel_batchbuffer_free(batch);
241 drm_intel_bufmgr_destroy(bufmgr);