tests/gem_stress.c

   1 /*
   2  * Copyright © 2011 Daniel Vetter
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Daniel Vetter <daniel.vetter@ffwll.ch>
  25  *
  26  * Partially based upon gem_tiled_fence_blits.c
  27  */
  28
  29 /** @file gem_stress.c
  30  *
  31  * This is a general gem coherency test. It's designed to eventually replicate
  32  * any possible sequence of access patterns. It works by copying a set of tiles
  33  * between two sets of backing buffer objects, randomly permutating the assinged
  34  * position on each copy operations.
  35  *
  36  * The copy operation are done in tiny portions (to reduce any race windows
  37  * for corruptions, hence increasing the chances for observing one) and are
  38  * constantly switched between all means to copy stuff (fenced blitter, unfenced
  39  * render, mmap, pwrite/read).
  40  *
  41  * After every complete move of a set tiling parameters of a buffer are randomly
  42  * changed to simulate the effects of libdrm caching.
  43  *
  44  * Buffers are 1mb big to nicely fit into fences on gen2/3. A few are further
  45  * split up to test relaxed fencing. Using this to push the average working set
  46  * size over the available gtt space forces objects to be mapped as unfenceable
  47  * (and as a side-effect tests gtt map/unmap coherency).
  48  *
  49  * In short: designed for maximum evilness.
  50  */
  51
  52 #include <stdlib.h>
  53 #include <sys/ioctl.h>
  54 #include <stdio.h>
  55 #include <string.h>
  56 #include <fcntl.h>
  57 #include <inttypes.h>
  58 #include <errno.h>
  59 #include <sys/stat.h>
  60 #include <sys/time.h>
  61
  62 #include <drm.h>
  63
  64 #include "ioctl_wrappers.h"
  65 #include "drmtest.h"
  66 #include "intel_bufmgr.h"
  67 #include "intel_batchbuffer.h"
  68 #include "intel_io.h"
  69 #include "intel_chipset.h"
  70 #include "igt_aux.h"
  71
  72 #define CMD_POLY_STIPPLE_OFFSET       0x7906
  73
  74 #define DUCTAPE 0xdead0001
  75 #define TILESZ  0xdead0002
  76 #define CHCK_RENDER 0xdead0003
  77
  78 /** TODO:
  79  * - beat on relaxed fencing (i.e. mappable/fenceable tracking in the kernel)
  80  * - render copy (to check fence tracking and cache coherency management by the
  81  *   kernel)
  82  * - multi-threading: probably just a wrapper script to launch multiple
  83  *   instances + an option to accordingly reduce the working set
  84  * - gen6 inter-ring coherency (needs render copy, first)
  85  * - variable buffer size
  86  * - add an option to fork a second process that randomly sends signals to the
  87  *   first one (to check consistency of the kernel recovery paths)
  88  */
  89
  90 drm_intel_bufmgr *bufmgr;
  91 struct intel_batchbuffer *batch;
  92 int drm_fd;
  93 int devid;
  94 int num_fences;
  95
  96 drm_intel_bo *busy_bo;
  97
  98 struct option_struct {
  99     unsigned scratch_buf_size;
 100     unsigned max_dimension;
 101     unsigned num_buffers;
 102     int trace_tile;
 103     int no_hw;
 104     int gpu_busy_load;
 105     int use_render;
 106     int use_blt;
 107     int forced_tiling;
 108     int use_cpu_maps;
 109     int total_rounds;
 110     int fail;
 111     int tiles_per_buf;
 112     int ducttape;
 113     int tile_size;
 114     int check_render_cpyfn;
 115     int use_signal_helper;
 116 };
 117
 118 struct option_struct options;
 119
 120 #define MAX_BUFS                4096
 121 #define SCRATCH_BUF_SIZE        1024*1024
 122 #define BUSY_BUF_SIZE           (256*4096)
 123 #define TILE_BYTES(size)        ((size)*(size)*sizeof(uint32_t))
 124
 125 static struct igt_buf buffers[2][MAX_BUFS];
 126 /* tile i is at logical position tile_permutation[i] */
 127 static unsigned *tile_permutation;
 128 static unsigned num_buffers = 0;
 129 static unsigned current_set = 0;
 130 static unsigned target_set = 0;
 131 static unsigned num_total_tiles = 0;
 132
 133 int fence_storm = 0;
 134 static int gpu_busy_load = 10;
 135
 136 struct {
 137         unsigned num_failed;
 138         unsigned max_failed_reads;
 139 } stats;
 140
 141 static void tile2xy(struct igt_buf *buf, unsigned tile, unsigned *x, unsigned *y)
 142 {
 143         igt_assert(tile < buf->num_tiles);
 144         *x = (tile*options.tile_size) % (buf->stride/sizeof(uint32_t));
 145         *y = ((tile*options.tile_size) / (buf->stride/sizeof(uint32_t))) * options.tile_size;
 146 }
 147
 148 static void emit_blt(drm_intel_bo *src_bo, uint32_t src_tiling, unsigned src_pitch,
 149                      unsigned src_x, unsigned src_y, unsigned w, unsigned h,
 150                      drm_intel_bo *dst_bo, uint32_t dst_tiling, unsigned dst_pitch,
 151                      unsigned dst_x, unsigned dst_y)
 152 {
 153         uint32_t cmd_bits = 0;
 154
 155         if (IS_965(devid) && src_tiling) {
 156                 src_pitch /= 4;
 157                 cmd_bits |= XY_SRC_COPY_BLT_SRC_TILED;
 158         }
 159
 160         if (IS_965(devid) && dst_tiling) {
 161                 dst_pitch /= 4;
 162                 cmd_bits |= XY_SRC_COPY_BLT_DST_TILED;
 163         }
 164
 165         /* copy lower half to upper half */
 166         BLIT_COPY_BATCH_START(devid, cmd_bits);
 167         OUT_BATCH((3 << 24) | /* 32 bits */
 168                   (0xcc << 16) | /* copy ROP */
 169                   dst_pitch);
 170         OUT_BATCH(dst_y << 16 | dst_x);
 171         OUT_BATCH((dst_y+h) << 16 | (dst_x+w));
 172         OUT_RELOC_FENCED(dst_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
 173         OUT_BATCH(src_y << 16 | src_x);
 174         OUT_BATCH(src_pitch);
 175         OUT_RELOC_FENCED(src_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
 176         ADVANCE_BATCH();
 177
 178         if (IS_GEN6(devid) || IS_GEN7(devid)) {
 179                 BEGIN_BATCH(3);
 180                 OUT_BATCH(XY_SETUP_CLIP_BLT_CMD);
 181                 OUT_BATCH(0);
 182                 OUT_BATCH(0);
 183                 ADVANCE_BATCH();
 184         }
 185 }
 186
 187 /* All this gem trashing wastes too much cpu time, so give the gpu something to
 188  * do to increase changes for races. */
 189 static void keep_gpu_busy(void)
 190 {
 191         int tmp;
 192
 193         tmp = 1 << gpu_busy_load;
 194         igt_assert(tmp <= 1024);
 195
 196         emit_blt(busy_bo, 0, 4096, 0, 0, tmp, 128,
 197                  busy_bo, 0, 4096, 0, 128);
 198 }
 199
 200 static void set_to_cpu_domain(struct igt_buf *buf, int writing)
 201 {
 202         gem_set_domain(drm_fd, buf->bo->handle, I915_GEM_DOMAIN_CPU,
 203                        writing ? I915_GEM_DOMAIN_CPU : 0);
 204 }
 205
 206 static unsigned int copyfunc_seq = 0;
 207 static void (*copyfunc)(struct igt_buf *src, unsigned src_x, unsigned src_y,
 208                         struct igt_buf *dst, unsigned dst_x, unsigned dst_y,
 209                         unsigned logical_tile_no);
 210
 211 /* stride, x, y in units of uint32_t! */
 212 static void cpucpy2d(uint32_t *src, unsigned src_stride, unsigned src_x, unsigned src_y,
 213                      uint32_t *dst, unsigned dst_stride, unsigned dst_x, unsigned dst_y,
 214                      unsigned logical_tile_no)
 215 {
 216         int i, j;
 217         int failed = 0;
 218
 219         for (i = 0; i < options.tile_size; i++) {
 220                 for (j = 0; j < options.tile_size; j++) {
 221                         unsigned dst_ofs = dst_x + j + dst_stride * (dst_y + i);
 222                         unsigned src_ofs = src_x + j + src_stride * (src_y + i);
 223                         unsigned expect = logical_tile_no*options.tile_size*options.tile_size
 224                             + i*options.tile_size + j;
 225                         uint32_t tmp = src[src_ofs];
 226                         if (tmp != expect) {
 227                             igt_info("mismatch at tile %i pos %i, read %i, expected %i, diff %i\n", logical_tile_no, i * options.tile_size + j, tmp, expect, (int)tmp - expect);
 228                             igt_fail_on(options.trace_tile >= 0 && options.fail);
 229                             failed++;
 230                         }
 231                         /* when not aborting, correct any errors */
 232                         dst[dst_ofs] = expect;
 233                 }
 234         }
 235         igt_fail_on(failed && options.fail);
 236
 237         if (failed > stats.max_failed_reads)
 238                 stats.max_failed_reads = failed;
 239         if (failed)
 240                 stats.num_failed++;
 241 }
 242
 243 static void cpu_copyfunc(struct igt_buf *src, unsigned src_x, unsigned src_y,
 244                          struct igt_buf *dst, unsigned dst_x, unsigned dst_y,
 245                          unsigned logical_tile_no)
 246 {
 247         igt_assert(batch->ptr == batch->buffer);
 248
 249         if (options.ducttape)
 250                 drm_intel_bo_wait_rendering(dst->bo);
 251
 252         if (options.use_cpu_maps) {
 253                 set_to_cpu_domain(src, 0);
 254                 set_to_cpu_domain(dst, 1);
 255         }
 256
 257         cpucpy2d(src->data, src->stride/sizeof(uint32_t), src_x, src_y,
 258                  dst->data, dst->stride/sizeof(uint32_t), dst_x, dst_y,
 259                  logical_tile_no);
 260 }
 261
 262 static void prw_copyfunc(struct igt_buf *src, unsigned src_x, unsigned src_y,
 263                          struct igt_buf *dst, unsigned dst_x, unsigned dst_y,
 264                          unsigned logical_tile_no)
 265 {
 266         uint32_t tmp_tile[options.tile_size*options.tile_size];
 267         int i;
 268
 269         igt_assert(batch->ptr == batch->buffer);
 270
 271         if (options.ducttape)
 272                 drm_intel_bo_wait_rendering(dst->bo);
 273
 274         if (src->tiling == I915_TILING_NONE) {
 275                 for (i = 0; i < options.tile_size; i++) {
 276                         unsigned ofs = src_x*sizeof(uint32_t) + src->stride*(src_y + i);
 277                         drm_intel_bo_get_subdata(src->bo, ofs,
 278                                                  options.tile_size*sizeof(uint32_t),
 279                                                  tmp_tile + options.tile_size*i);
 280                 }
 281         } else {
 282                 if (options.use_cpu_maps)
 283                         set_to_cpu_domain(src, 0);
 284
 285                 cpucpy2d(src->data, src->stride/sizeof(uint32_t), src_x, src_y,
 286                          tmp_tile, options.tile_size, 0, 0, logical_tile_no);
 287         }
 288
 289         if (dst->tiling == I915_TILING_NONE) {
 290                 for (i = 0; i < options.tile_size; i++) {
 291                         unsigned ofs = dst_x*sizeof(uint32_t) + dst->stride*(dst_y + i);
 292                         drm_intel_bo_subdata(dst->bo, ofs,
 293                                              options.tile_size*sizeof(uint32_t),
 294                                              tmp_tile + options.tile_size*i);
 295                 }
 296         } else {
 297                 if (options.use_cpu_maps)
 298                         set_to_cpu_domain(dst, 1);
 299
 300                 cpucpy2d(tmp_tile, options.tile_size, 0, 0,
 301                          dst->data, dst->stride/sizeof(uint32_t), dst_x, dst_y,
 302                          logical_tile_no);
 303         }
 304 }
 305
 306 static void blitter_copyfunc(struct igt_buf *src, unsigned src_x, unsigned src_y,
 307                              struct igt_buf *dst, unsigned dst_x, unsigned dst_y,
 308                              unsigned logical_tile_no)
 309 {
 310         static unsigned keep_gpu_busy_counter = 0;
 311
 312         /* check both edges of the fence usage */
 313         if (keep_gpu_busy_counter & 1 && !fence_storm)
 314                 keep_gpu_busy();
 315
 316         emit_blt(src->bo, src->tiling, src->stride, src_x, src_y,
 317                  options.tile_size, options.tile_size,
 318                  dst->bo, dst->tiling, dst->stride, dst_x, dst_y);
 319
 320         if (!(keep_gpu_busy_counter & 1) && !fence_storm)
 321                 keep_gpu_busy();
 322
 323         keep_gpu_busy_counter++;
 324
 325         if (src->tiling)
 326                 fence_storm--;
 327         if (dst->tiling)
 328                 fence_storm--;
 329
 330         if (fence_storm <= 1) {
 331                 fence_storm = 0;
 332                 intel_batchbuffer_flush(batch);
 333         }
 334 }
 335
 336 static void render_copyfunc(struct igt_buf *src, unsigned src_x, unsigned src_y,
 337                             struct igt_buf *dst, unsigned dst_x, unsigned dst_y,
 338                             unsigned logical_tile_no)
 339 {
 340         static unsigned keep_gpu_busy_counter = 0;
 341         igt_render_copyfunc_t rendercopy = igt_get_render_copyfunc(devid);
 342
 343         /* check both edges of the fence usage */
 344         if (keep_gpu_busy_counter & 1)
 345                 keep_gpu_busy();
 346
 347         if (rendercopy) {
 348                 /*
 349                  * Flush outstanding blts so that they don't end up on
 350                  * the render ring when that's not allowed (gen6+).
 351                  */
 352                 intel_batchbuffer_flush(batch);
 353                 rendercopy(batch, NULL, src, src_x, src_y,
 354                      options.tile_size, options.tile_size,
 355                      dst, dst_x, dst_y);
 356         } else
 357                 blitter_copyfunc(src, src_x, src_y,
 358                                  dst, dst_x, dst_y,
 359                                  logical_tile_no);
 360         if (!(keep_gpu_busy_counter & 1))
 361                 keep_gpu_busy();
 362
 363         keep_gpu_busy_counter++;
 364         intel_batchbuffer_flush(batch);
 365 }
 366
 367 static void next_copyfunc(int tile)
 368 {
 369         if (fence_storm) {
 370                 if (tile == options.trace_tile)
 371                         igt_info(" using fence storm\n");
 372                 return;
 373         }
 374
 375         if (copyfunc_seq % 61 == 0
 376                         && options.forced_tiling != I915_TILING_NONE) {
 377                 if (tile == options.trace_tile)
 378                         igt_info(" using fence storm\n");
 379                 fence_storm = num_fences;
 380                 copyfunc = blitter_copyfunc;
 381         } else if (copyfunc_seq % 17 == 0) {
 382                 if (tile == options.trace_tile)
 383                         igt_info(" using cpu\n");
 384                 copyfunc = cpu_copyfunc;
 385         } else if (copyfunc_seq % 19 == 0) {
 386                 if (tile == options.trace_tile)
 387                         igt_info(" using prw\n");
 388                 copyfunc = prw_copyfunc;
 389         } else if (copyfunc_seq % 3 == 0 && options.use_render) {
 390                 if (tile == options.trace_tile)
 391                         igt_info(" using render\n");
 392                 copyfunc = render_copyfunc;
 393         } else if (options.use_blt){
 394                 if (tile == options.trace_tile)
 395                         igt_info(" using blitter\n");
 396                 copyfunc = blitter_copyfunc;
 397         } else if (options.use_render){
 398                 if (tile == options.trace_tile)
 399                         igt_info(" using render\n");
 400                 copyfunc = render_copyfunc;
 401         } else {
 402                 copyfunc = cpu_copyfunc;
 403         }
 404
 405         copyfunc_seq++;
 406 }
 407
 408 static void fan_out(void)
 409 {
 410         uint32_t tmp_tile[options.tile_size*options.tile_size];
 411         uint32_t seq = 0;
 412         int i, k;
 413         unsigned tile, buf_idx, x, y;
 414
 415         for (i = 0; i < num_total_tiles; i++) {
 416                 tile = i;
 417                 buf_idx = tile / options.tiles_per_buf;
 418                 tile %= options.tiles_per_buf;
 419
 420                 tile2xy(&buffers[current_set][buf_idx], tile, &x, &y);
 421
 422                 for (k = 0; k < options.tile_size*options.tile_size; k++)
 423                         tmp_tile[k] = seq++;
 424
 425                 if (options.use_cpu_maps)
 426                         set_to_cpu_domain(&buffers[current_set][buf_idx], 1);
 427
 428                 cpucpy2d(tmp_tile, options.tile_size, 0, 0,
 429                          buffers[current_set][buf_idx].data,
 430                          buffers[current_set][buf_idx].stride / sizeof(uint32_t),
 431                          x, y, i);
 432         }
 433
 434         for (i = 0; i < num_total_tiles; i++)
 435                 tile_permutation[i] = i;
 436 }
 437
 438 static void fan_in_and_check(void)
 439 {
 440         uint32_t tmp_tile[options.tile_size*options.tile_size];
 441         unsigned tile, buf_idx, x, y;
 442         int i;
 443         for (i = 0; i < num_total_tiles; i++) {
 444                 tile = tile_permutation[i];
 445                 buf_idx = tile / options.tiles_per_buf;
 446                 tile %= options.tiles_per_buf;
 447
 448                 tile2xy(&buffers[current_set][buf_idx], tile, &x, &y);
 449
 450                 if (options.use_cpu_maps)
 451                         set_to_cpu_domain(&buffers[current_set][buf_idx], 0);
 452
 453                 cpucpy2d(buffers[current_set][buf_idx].data,
 454                          buffers[current_set][buf_idx].stride / sizeof(uint32_t),
 455                          x, y,
 456                          tmp_tile, options.tile_size, 0, 0,
 457                          i);
 458         }
 459 }
 460
 461 static void sanitize_stride(struct igt_buf *buf)
 462 {
 463
 464         if (igt_buf_height(buf) > options.max_dimension)
 465                 buf->stride = buf->size / options.max_dimension;
 466
 467         if (igt_buf_height(buf) < options.tile_size)
 468                 buf->stride = buf->size / options.tile_size;
 469
 470         if (igt_buf_width(buf) < options.tile_size)
 471                 buf->stride = options.tile_size * sizeof(uint32_t);
 472
 473         igt_assert(buf->stride <= 8192);
 474         igt_assert(igt_buf_width(buf) <= options.max_dimension);
 475         igt_assert(igt_buf_height(buf) <= options.max_dimension);
 476
 477         igt_assert(igt_buf_width(buf) >= options.tile_size);
 478         igt_assert(igt_buf_height(buf) >= options.tile_size);
 479
 480 }
 481
 482 static void init_buffer(struct igt_buf *buf, unsigned size)
 483 {
 484         buf->bo = drm_intel_bo_alloc(bufmgr, "tiled bo", size, 4096);
 485         buf->size = size;
 486         igt_assert(buf->bo);
 487         buf->tiling = I915_TILING_NONE;
 488         buf->stride = 4096;
 489
 490         sanitize_stride(buf);
 491
 492         if (options.no_hw)
 493                 buf->data = malloc(size);
 494         else {
 495                 if (options.use_cpu_maps)
 496                         drm_intel_bo_map(buf->bo, 1);
 497                 else
 498                         drm_intel_gem_bo_map_gtt(buf->bo);
 499                 buf->data = buf->bo->virtual;
 500         }
 501
 502         buf->num_tiles = options.tiles_per_buf;
 503 }
 504
 505 static void exchange_buf(void *array, unsigned i, unsigned j)
 506 {
 507         struct igt_buf *buf_arr, tmp;
 508         buf_arr = array;
 509
 510         memcpy(&tmp, &buf_arr[i], sizeof(struct igt_buf));
 511         memcpy(&buf_arr[i], &buf_arr[j], sizeof(struct igt_buf));
 512         memcpy(&buf_arr[j], &tmp, sizeof(struct igt_buf));
 513 }
 514
 515
 516 static void init_set(unsigned set)
 517 {
 518         long int r;
 519         int i;
 520
 521         igt_permute_array(buffers[set], num_buffers, exchange_buf);
 522
 523         if (current_set == 1 && options.gpu_busy_load == 0) {
 524                 gpu_busy_load++;
 525                 if (gpu_busy_load > 10)
 526                         gpu_busy_load = 6;
 527         }
 528
 529         for (i = 0; i < num_buffers; i++) {
 530                 r = random();
 531                 if ((r & 3) != 0)
 532                     continue;
 533                 r >>= 2;
 534
 535                 if ((r & 3) != 0)
 536                         buffers[set][i].tiling = I915_TILING_X;
 537                 else
 538                         buffers[set][i].tiling = I915_TILING_NONE;
 539                 r >>= 2;
 540                 if (options.forced_tiling >= 0)
 541                         buffers[set][i].tiling = options.forced_tiling;
 542
 543                 if (buffers[set][i].tiling == I915_TILING_NONE) {
 544                         /* min 64 byte stride */
 545                         r %= 8;
 546                         buffers[set][i].stride = 64 * (1 << r);
 547                 } else if (IS_GEN2(devid)) {
 548                         /* min 128 byte stride */
 549                         r %= 7;
 550                         buffers[set][i].stride = 128 * (1 << r);
 551                 } else {
 552                         /* min 512 byte stride */
 553                         r %= 5;
 554                         buffers[set][i].stride = 512 * (1 << r);
 555                 }
 556
 557                 sanitize_stride(&buffers[set][i]);
 558
 559                 gem_set_tiling(drm_fd, buffers[set][i].bo->handle,
 560                                buffers[set][i].tiling,
 561                                buffers[set][i].stride);
 562
 563                 if (options.trace_tile != -1 && i == options.trace_tile/options.tiles_per_buf)
 564                         igt_info("changing buffer %i containing tile %i: tiling %i, stride %i\n", i, options.trace_tile, buffers[set][i].tiling, buffers[set][i].stride);
 565         }
 566 }
 567
 568 static void exchange_uint(void *array, unsigned i, unsigned j)
 569 {
 570         unsigned *i_arr = array;
 571         unsigned i_tmp;
 572
 573         i_tmp = i_arr[i];
 574         i_arr[i] = i_arr[j];
 575         i_arr[j] = i_tmp;
 576 }
 577
 578 static void copy_tiles(unsigned *permutation)
 579 {
 580         unsigned src_tile, src_buf_idx, src_x, src_y;
 581         unsigned dst_tile, dst_buf_idx, dst_x, dst_y;
 582         struct igt_buf *src_buf, *dst_buf;
 583         int i, idx;
 584         for (i = 0; i < num_total_tiles; i++) {
 585                 /* tile_permutation is independent of current_permutation, so
 586                  * abuse it to randomize the order of the src bos */
 587                 idx  = tile_permutation[i];
 588                 src_buf_idx = idx / options.tiles_per_buf;
 589                 src_tile = idx % options.tiles_per_buf;
 590                 src_buf = &buffers[current_set][src_buf_idx];
 591
 592                 tile2xy(src_buf, src_tile, &src_x, &src_y);
 593
 594                 dst_buf_idx = permutation[idx] / options.tiles_per_buf;
 595                 dst_tile = permutation[idx] % options.tiles_per_buf;
 596                 dst_buf = &buffers[target_set][dst_buf_idx];
 597
 598                 tile2xy(dst_buf, dst_tile, &dst_x, &dst_y);
 599
 600                 if (options.trace_tile == i)
 601                         igt_info("copying tile %i from %i (%i, %i) to %i (%i, %i)", i, tile_permutation[i], src_buf_idx, src_tile, permutation[idx], dst_buf_idx, dst_tile);
 602
 603                 if (options.no_hw) {
 604                         cpucpy2d(src_buf->data,
 605                                  src_buf->stride / sizeof(uint32_t),
 606                                  src_x, src_y,
 607                                  dst_buf->data,
 608                                  dst_buf->stride / sizeof(uint32_t),
 609                                  dst_x, dst_y,
 610                                  i);
 611                 } else {
 612                         next_copyfunc(i);
 613
 614                         copyfunc(src_buf, src_x, src_y, dst_buf, dst_x, dst_y,
 615                                  i);
 616                 }
 617         }
 618
 619         intel_batchbuffer_flush(batch);
 620 }
 621
 622 static void sanitize_tiles_per_buf(void)
 623 {
 624         if (options.tiles_per_buf > options.scratch_buf_size / TILE_BYTES(options.tile_size))
 625                 options.tiles_per_buf = options.scratch_buf_size / TILE_BYTES(options.tile_size);
 626 }
 627
 628 static int parse_options(int opt, int opt_index)
 629 {
 630         int tmp;
 631
 632         switch(opt) {
 633                 case 'd':
 634                         options.no_hw = 1;
 635                         igt_info("no-hw debug mode\n");
 636                         break;
 637                 case 'S':
 638                         options.use_signal_helper = 0;
 639                         igt_info("disabling that pesky nuisance who keeps interrupting us\n");
 640                         break;
 641                 case 's':
 642                         tmp = atoi(optarg);
 643                         if (tmp < options.tile_size*8192)
 644                                 igt_info("scratch buffer size needs to be at least %i\n", options.tile_size * 8192);
 645                         else if (tmp & (tmp - 1)) {
 646                                 igt_info("scratch buffer size needs to be a power-of-two\n");
 647                         } else {
 648                                 igt_info("fixed scratch buffer size to %u\n", tmp);
 649                                 options.scratch_buf_size = tmp;
 650                                 sanitize_tiles_per_buf();
 651                         }
 652                         break;
 653                 case 'g':
 654                         tmp = atoi(optarg);
 655                         if (tmp < 0 || tmp > 10)
 656                                 igt_info("gpu busy load needs to be bigger than 0 and smaller than 10\n");
 657                         else {
 658                                 igt_info("gpu busy load factor set to %i\n", tmp);
 659                                 gpu_busy_load = options.gpu_busy_load = tmp;
 660                         }
 661                         break;
 662                 case 'c':
 663                         options.num_buffers = atoi(optarg);
 664                         igt_info("buffer count set to %i\n", options.num_buffers);
 665                         break;
 666                 case 't':
 667                         options.trace_tile = atoi(optarg);
 668                         igt_info("tracing tile %i\n", options.trace_tile);
 669                         break;
 670                 case 'r':
 671                         options.use_render = 0;
 672                         igt_info("disabling render copy\n");
 673                         break;
 674                 case 'b':
 675                         options.use_blt = 0;
 676                         igt_info("disabling blt copy\n");
 677                         break;
 678                 case 'u':
 679                         options.forced_tiling = I915_TILING_NONE;
 680                         igt_info("disabling tiling\n");
 681                         break;
 682                 case 'x':
 683                         if (options.use_cpu_maps) {
 684                                 igt_info("tiling not possible with cpu maps\n");
 685                         } else {
 686                                 options.forced_tiling = I915_TILING_X;
 687                                 igt_info("using only X-tiling\n");
 688                         }
 689                         break;
 690                 case 'm':
 691                         options.use_cpu_maps = 1;
 692                         options.forced_tiling = I915_TILING_NONE;
 693                         igt_info("disabling tiling\n");
 694                         break;
 695                 case 'o':
 696                         options.total_rounds = atoi(optarg);
 697                         igt_info("total rounds %i\n", options.total_rounds);
 698                         break;
 699                 case 'f':
 700                         options.fail = 0;
 701                         igt_info("not failing when detecting errors\n");
 702                         break;
 703                 case 'p':
 704                         options.tiles_per_buf = atoi(optarg);
 705                         igt_info("tiles per buffer %i\n", options.tiles_per_buf);
 706                         break;
 707                 case DUCTAPE:
 708                         options.ducttape = 0;
 709                         igt_info("applying duct-tape\n");
 710                         break;
 711                 case TILESZ:
 712                         options.tile_size = atoi(optarg);
 713                         sanitize_tiles_per_buf();
 714                         igt_info("til size %i\n", options.tile_size);
 715                         break;
 716                 case CHCK_RENDER:
 717                         options.check_render_cpyfn = 1;
 718                         igt_info("checking render copy function\n");
 719                         break;
 720         }
 721
 722         /* actually 32767, according to docs, but that kills our nice pot calculations. */
 723         options.max_dimension = 16*1024;
 724         if (options.use_render) {
 725                 if (IS_GEN2(devid) || IS_GEN3(devid))
 726                         options.max_dimension = 2048;
 727                 else
 728                         options.max_dimension = 8192;
 729         }
 730         igt_info("Limiting buffer to %dx%d\n", options.max_dimension, options.max_dimension);
 731
 732         return 0;
 733 }
 734
 735 static void init(void)
 736 {
 737         int i;
 738         unsigned tmp;
 739
 740         if (options.num_buffers == 0) {
 741                 tmp = gem_aperture_size(drm_fd);
 742                 tmp = tmp > 256*(1024*1024) ? 256*(1024*1024) : tmp;
 743                 num_buffers = 2 * tmp / options.scratch_buf_size / 3;
 744                 num_buffers /= 2;
 745                 igt_info("using %u buffers\n", num_buffers);
 746         } else
 747                 num_buffers = options.num_buffers;
 748
 749         bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
 750         drm_intel_bufmgr_gem_enable_reuse(bufmgr);
 751         drm_intel_bufmgr_gem_enable_fenced_relocs(bufmgr);
 752         num_fences = gem_available_fences(drm_fd);
 753         igt_assert(num_fences > 4);
 754         batch = intel_batchbuffer_alloc(bufmgr, devid);
 755
 756         busy_bo = drm_intel_bo_alloc(bufmgr, "tiled bo", BUSY_BUF_SIZE, 4096);
 757         if (options.forced_tiling >= 0)
 758                 gem_set_tiling(drm_fd, busy_bo->handle, options.forced_tiling, 4096);
 759
 760         for (i = 0; i < num_buffers; i++) {
 761                 init_buffer(&buffers[0][i], options.scratch_buf_size);
 762                 init_buffer(&buffers[1][i], options.scratch_buf_size);
 763
 764                 num_total_tiles += buffers[0][i].num_tiles;
 765         }
 766         current_set = 0;
 767
 768         /* just in case it helps reproducability */
 769         srandom(0xdeadbeef);
 770 }
 771
 772 static void check_render_copyfunc(void)
 773 {
 774         struct igt_buf src, dst;
 775         uint32_t *ptr;
 776         int i, j, pass;
 777
 778         if (!options.check_render_cpyfn)
 779                 return;
 780
 781         init_buffer(&src, options.scratch_buf_size);
 782         init_buffer(&dst, options.scratch_buf_size);
 783
 784         for (pass = 0; pass < 16; pass++) {
 785                 int sx = random() % (igt_buf_width(&src)-options.tile_size);
 786                 int sy = random() % (igt_buf_height(&src)-options.tile_size);
 787                 int dx = random() % (igt_buf_width(&dst)-options.tile_size);
 788                 int dy = random() % (igt_buf_height(&dst)-options.tile_size);
 789
 790                 if (options.use_cpu_maps)
 791                         set_to_cpu_domain(&src, 1);
 792
 793                 memset(src.data, 0xff, options.scratch_buf_size);
 794                 for (j = 0; j < options.tile_size; j++) {
 795                         ptr = (uint32_t*)((char *)src.data + sx*4 + (sy+j) * src.stride);
 796                         for (i = 0; i < options.tile_size; i++)
 797                                 ptr[i] = j * options.tile_size + i;
 798                 }
 799
 800                 render_copyfunc(&src, sx, sy, &dst, dx, dy, 0);
 801
 802                 if (options.use_cpu_maps)
 803                         set_to_cpu_domain(&dst, 0);
 804
 805                 for (j = 0; j < options.tile_size; j++) {
 806                         ptr = (uint32_t*)((char *)dst.data + dx*4 + (dy+j) * dst.stride);
 807                         for (i = 0; i < options.tile_size; i++)
 808                                 if (ptr[i] != j * options.tile_size + i) {
 809                                         igt_info("render copyfunc mismatch at (%d, %d): found %d, expected %d\n", i, j, ptr[i], j * options.tile_size + i);
 810                                 }
 811                 }
 812         }
 813 }
 814
 815
 816 int main(int argc, char **argv)
 817 {
 818         int i, j;
 819         unsigned *current_permutation, *tmp_permutation;
 820         static struct option long_options[] = {
 821                 {"no-hw", 0, 0, 'd'},
 822                 {"buf-size", 1, 0, 's'},
 823                 {"gpu-busy-load", 1, 0, 'g'},
 824                 {"no-signals", 0, 0, 'S'},
 825                 {"buffer-count", 1, 0, 'c'},
 826                 {"trace-tile", 1, 0, 't'},
 827                 {"disable-blt", 0, 0, 'b'},
 828                 {"disable-render", 0, 0, 'r'},
 829                 {"untiled", 0, 0, 'u'},
 830                 {"x-tiled", 0, 0, 'x'},
 831                 {"use-cpu-maps", 0, 0, 'm'},
 832                 {"rounds", 1, 0, 'o'},
 833                 {"no-fail", 0, 0, 'f'},
 834                 {"tiles-per-buf", 0, 0, 'p'},
 835                 {"remove-duct-tape", 0, 0, DUCTAPE},
 836                 {"tile-size", 1, 0, TILESZ},
 837                 {"check-render-cpyfn", 0, 0, CHCK_RENDER},
 838                 {NULL, 0, 0, 0},
 839         };
 840
 841         options.scratch_buf_size = 256*4096;
 842         options.no_hw = 0;
 843         options.use_signal_helper = 1;
 844         options.gpu_busy_load = 0;
 845         options.num_buffers = 0;
 846         options.trace_tile = -1;
 847         options.use_render = 1;
 848         options.use_blt = 1;
 849         options.forced_tiling = -1;
 850         options.use_cpu_maps = 0;
 851         options.total_rounds = 512;
 852         options.fail = 1;
 853         options.ducttape = 1;
 854         options.tile_size = 16;
 855         options.tiles_per_buf = options.scratch_buf_size / TILE_BYTES(options.tile_size);
 856         options.check_render_cpyfn = 0;
 857
 858         igt_simple_init_parse_opts(argc, argv,"ds:g:c:t:rbuxmo:fp:",
 859                                    long_options, NULL, parse_options);
 860
 861         drm_fd = drm_open_any();
 862         devid = intel_get_drm_devid(drm_fd);
 863
 864         /* start our little helper early before too may allocations occur */
 865         if (options.use_signal_helper)
 866                 igt_fork_signal_helper();
 867
 868         init();
 869
 870         check_render_copyfunc();
 871
 872         tile_permutation = malloc(num_total_tiles*sizeof(uint32_t));
 873         current_permutation = malloc(num_total_tiles*sizeof(uint32_t));
 874         tmp_permutation = malloc(num_total_tiles*sizeof(uint32_t));
 875         igt_assert(tile_permutation);
 876         igt_assert(current_permutation);
 877         igt_assert(tmp_permutation);
 878
 879         fan_out();
 880
 881         for (i = 0; i < options.total_rounds; i++) {
 882                 igt_info("round %i\n", i);
 883                 if (i % 64 == 63) {
 884                         fan_in_and_check();
 885                         igt_info("everything correct after %i rounds\n", i + 1);
 886                 }
 887
 888                 target_set = (current_set + 1) & 1;
 889                 init_set(target_set);
 890
 891                 for (j = 0; j < num_total_tiles; j++)
 892                         current_permutation[j] = j;
 893                 igt_permute_array(current_permutation, num_total_tiles, exchange_uint);
 894
 895                 copy_tiles(current_permutation);
 896
 897                 memcpy(tmp_permutation, tile_permutation, sizeof(unsigned)*num_total_tiles);
 898
 899                 /* accumulate the permutations */
 900                 for (j = 0; j < num_total_tiles; j++)
 901                         tile_permutation[j] = current_permutation[tmp_permutation[j]];
 902
 903                 current_set = target_set;
 904         }
 905
 906         fan_in_and_check();
 907
 908         igt_info("num failed tiles %u, max incoherent bytes %zd\n", stats.num_failed, stats.max_failed_reads * sizeof(uint32_t));
 909
 910         intel_batchbuffer_free(batch);
 911         drm_intel_bufmgr_destroy(bufmgr);
 912
 913         close(drm_fd);
 914
 915         igt_stop_signal_helper();
 916
 917         return 0;
 918 }