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24 * Xiang, Haihao <haihao.xiang@intel.com> (based on gem_store_dw_loop_*)
37 #include "ioctl_wrappers.h"
39 #include "intel_bufmgr.h"
40 #include "intel_batchbuffer.h"
42 #include "intel_chipset.h"
44 #define LOCAL_I915_EXEC_VEBOX (4<<0)
46 static drm_intel_bufmgr *bufmgr;
47 struct intel_batchbuffer *batch;
48 static drm_intel_bo *target_buffer;
51 * Testcase: Basic vebox MI check using MI_STORE_DATA_IMM
55 store_dword_loop(int divider)
60 igt_info("running storedw loop on blt with stall every %i batch\n", divider);
62 cmd = MI_STORE_DWORD_IMM;
64 for (i = 0; i < SLOW_QUICK(0x2000, 0x10); i++) {
67 if (intel_gen(batch->devid) < 8)
68 OUT_BATCH(0); /* reserved */
69 OUT_RELOC(target_buffer, I915_GEM_DOMAIN_INSTRUCTION,
70 I915_GEM_DOMAIN_INSTRUCTION, 0);
71 BLIT_RELOC_UDW(batch->devid);
75 intel_batchbuffer_flush_on_ring(batch, LOCAL_I915_EXEC_VEBOX);
80 drm_intel_bo_map(target_buffer, 0);
82 buf = target_buffer->virtual;
83 igt_assert_eq_u32(buf[0], val);
85 drm_intel_bo_unmap(target_buffer);
91 drm_intel_bo_map(target_buffer, 0);
92 buf = target_buffer->virtual;
94 igt_info("completed %d writes successfully, current value: 0x%08x\n", i,
96 drm_intel_bo_unmap(target_buffer);
105 igt_require(gem_has_vebox(fd));
106 igt_require(gem_uses_aliasing_ppgtt(fd));
108 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
110 drm_intel_bufmgr_gem_enable_reuse(bufmgr);
112 batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
115 target_buffer = drm_intel_bo_alloc(bufmgr, "target bo", 4096, 4096);
116 igt_require(target_buffer);
120 if (!igt_run_in_simulation()) {
125 drm_intel_bo_unreference(target_buffer);
126 intel_batchbuffer_free(batch);
127 drm_intel_bufmgr_destroy(bufmgr);