2 * Copyright © 2009 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Jesse Barnes <jbarnes@virtuousgeek.org> (based on gem_bad_blit.c)
38 #include "ioctl_wrappers.h"
40 #include "intel_bufmgr.h"
41 #include "intel_batchbuffer.h"
43 #include "intel_chipset.h"
45 static drm_intel_bufmgr *bufmgr;
46 struct intel_batchbuffer *batch;
47 static drm_intel_bo *target_buffer;
48 static int has_ppgtt = 0;
51 * Testcase: Basic render MI check using MI_STORE_DATA_IMM
55 emit_store_dword_imm(int devid, drm_intel_bo *dest, uint32_t val)
58 cmd = MI_STORE_DWORD_IMM;
60 cmd |= MI_MEM_VIRTUAL;
62 if (intel_gen(devid) >= 8) {
65 OUT_RELOC(dest, I915_GEM_DOMAIN_INSTRUCTION,
66 I915_GEM_DOMAIN_INSTRUCTION, 0);
73 OUT_BATCH(0); /* reserved */
74 OUT_RELOC(dest, I915_GEM_DOMAIN_INSTRUCTION,
75 I915_GEM_DOMAIN_INSTRUCTION, 0);
82 store_dword_loop(int devid, int divider)
87 igt_info("running storedw loop on render with stall every %i batch\n", divider);
89 for (i = 0; i < SLOW_QUICK(0x100000, 0x10); i++) {
90 emit_store_dword_imm(devid, target_buffer, val);
91 intel_batchbuffer_flush_on_ring(batch, 0);
96 drm_intel_bo_map(target_buffer, 0);
98 buf = target_buffer->virtual;
99 igt_assert_f(buf[0] == val,
100 "value mismatch: cur 0x%08x, stored 0x%08x\n",
103 drm_intel_bo_unmap(target_buffer);
109 drm_intel_bo_map(target_buffer, 0);
110 buf = target_buffer->virtual;
112 igt_info("completed %d writes successfully, current value: 0x%08x\n", i,
114 drm_intel_bo_unmap(target_buffer);
123 devid = intel_get_drm_devid(fd);
125 has_ppgtt = gem_uses_aliasing_ppgtt(fd);
127 igt_skip_on_f(intel_gen(devid) < 6,
128 "MI_STORE_DATA can only use GTT address on gen4+/g33 and "
129 "needs snoopable mem on pre-gen6\n");
131 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
133 drm_intel_bufmgr_gem_enable_reuse(bufmgr);
135 batch = intel_batchbuffer_alloc(bufmgr, devid);
138 target_buffer = drm_intel_bo_alloc(bufmgr, "target bo", 4096, 4096);
139 igt_assert(target_buffer);
141 store_dword_loop(devid, 1);
142 store_dword_loop(devid, 2);
143 if (!igt_run_in_simulation()) {
144 store_dword_loop(devid, 3);
145 store_dword_loop(devid, 5);
148 drm_intel_bo_unreference(target_buffer);
149 intel_batchbuffer_free(batch);
150 drm_intel_bufmgr_destroy(bufmgr);