tests/gem_storedw_batches_loop.c

   1 /*
   2  * Copyright © 2009 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Jesse Barnes <jbarnes@virtuousgeek.org> (based on gem_bad_blit.c)
  26  *
  27  */
  28
  29 #include <stdlib.h>
  30 #include <stdio.h>
  31 #include <string.h>
  32 #include <fcntl.h>
  33 #include <inttypes.h>
  34 #include <errno.h>
  35 #include <sys/stat.h>
  36 #include <sys/time.h>
  37 #include "drm.h"
  38 #include "ioctl_wrappers.h"
  39 #include "drmtest.h"
  40 #include "intel_bufmgr.h"
  41 #include "intel_chipset.h"
  42 #include "intel_batchbuffer.h"
  43 #include "intel_io.h"
  44
  45 static drm_intel_bufmgr *bufmgr;
  46 static drm_intel_bo *target_bo;
  47 static int has_ppgtt = 0;
  48
  49 #define SECURE_DISPATCH (1<<0)
  50
  51 /* Like the store dword test, but we create new command buffers each time */
  52 static void
  53 store_dword_loop(int divider, unsigned flags)
  54 {
  55         int cmd, i, val = 0;
  56         uint32_t *buf;
  57         drm_intel_bo *cmd_bo;
  58
  59         igt_info("running storedw loop with stall every %i batch\n", divider);
  60
  61         cmd = MI_STORE_DWORD_IMM;
  62         if (!has_ppgtt)
  63                 cmd |= MI_MEM_VIRTUAL;
  64
  65         for (i = 0; i < SLOW_QUICK(0x2000, 4); i++) {
  66                 int j = 0;
  67                 int cmd_address_offset;
  68                 cmd_bo = drm_intel_bo_alloc(bufmgr, "cmd bo", 4096, 4096);
  69                 igt_assert(cmd_bo);
  70
  71                 /* Upload through cpu mmaps to make sure we don't have a gtt
  72                  * mapping which could paper over secure batch submission
  73                  * failing to bind that. */
  74                 drm_intel_bo_map(cmd_bo, 1);
  75                 buf = cmd_bo->virtual;
  76
  77                 buf[j++] = cmd;
  78                 if (intel_gen(drm_intel_bufmgr_gem_get_devid(bufmgr)) >= 8) {
  79                         cmd_address_offset = j * 4;
  80                         buf[j++] = target_bo->offset;
  81                         buf[j++] = 0;
  82                 } else {
  83                         buf[j++] = 0;
  84                         cmd_address_offset = j * 4;
  85                         buf[j++] = target_bo->offset;
  86                 }
  87                 igt_assert(j > 0);
  88                 buf[j++] = 0x42000000 + val;
  89
  90                 igt_assert(drm_intel_bo_references(cmd_bo, target_bo) == 0);
  91
  92                 igt_assert(drm_intel_bo_emit_reloc(cmd_bo, cmd_address_offset, target_bo, 0,
  93                                               I915_GEM_DOMAIN_INSTRUCTION,
  94                                               I915_GEM_DOMAIN_INSTRUCTION) == 0);
  95                 buf[j++] = MI_BATCH_BUFFER_END;
  96                 buf[j++] = MI_BATCH_BUFFER_END;
  97
  98                 drm_intel_bo_unmap(cmd_bo);
  99
 100                 igt_assert(drm_intel_bo_references(cmd_bo, target_bo) == 1);
 101
 102 #define LOCAL_I915_EXEC_SECURE (1<<9)
 103                 igt_assert(drm_intel_bo_mrb_exec(cmd_bo, j * 4, NULL, 0, 0,
 104                                             I915_EXEC_BLT |
 105                                             (flags & SECURE_DISPATCH ? LOCAL_I915_EXEC_SECURE : 0))
 106                            == 0);
 107
 108                 if (i % divider != 0)
 109                         goto cont;
 110
 111                 drm_intel_bo_wait_rendering(cmd_bo);
 112
 113                 drm_intel_bo_map(target_bo, 1);
 114
 115                 buf = target_bo->virtual;
 116                 igt_assert_f(buf[0] == (0x42000000 | val),
 117                              "value mismatch: cur 0x%08x, stored 0x%08x\n",
 118                              buf[0], 0x42000000 | val);
 119
 120                 buf[0] = 0; /* let batch write it again */
 121                 drm_intel_bo_unmap(target_bo);
 122
 123 cont:
 124                 drm_intel_bo_unreference(cmd_bo);
 125
 126                 val++;
 127         }
 128
 129         igt_info("completed %d writes successfully\n", i);
 130 }
 131
 132 int fd;
 133 int devid;
 134
 135 igt_main
 136 {
 137         igt_skip_on_simulation();
 138
 139         igt_fixture {
 140                 fd = drm_open_any();
 141                 devid = intel_get_drm_devid(fd);
 142
 143                 has_ppgtt = gem_uses_aliasing_ppgtt(fd);
 144
 145                 /* storedw needs gtt address on gen4+/g33 and snoopable memory.
 146                  * Strictly speaking we could implement this now ... */
 147                 igt_require(intel_gen(devid) >= 6);
 148
 149                 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
 150                 igt_assert(bufmgr);
 151
 152                 //      drm_intel_bufmgr_gem_enable_reuse(bufmgr);
 153
 154                 target_bo = drm_intel_bo_alloc(bufmgr, "target bo", 4096, 4096);
 155                 igt_assert(target_bo);
 156         }
 157
 158         igt_subtest("normal") {
 159                 store_dword_loop(1, 0);
 160                 store_dword_loop(2, 0);
 161                 store_dword_loop(3, 0);
 162                 store_dword_loop(5, 0);
 163         }
 164
 165         igt_subtest("secure-dispatch") {
 166                 store_dword_loop(1, SECURE_DISPATCH);
 167                 store_dword_loop(2, SECURE_DISPATCH);
 168                 store_dword_loop(3, SECURE_DISPATCH);
 169                 store_dword_loop(5, SECURE_DISPATCH);
 170         }
 171
 172         igt_fixture {
 173                 drm_intel_bo_unreference(target_bo);
 174                 drm_intel_bufmgr_destroy(bufmgr);
 175
 176                 close(fd);
 177         }
 178 }