2 * Copyright © 2012 Intel Corporation
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11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Vetter <daniel.vetter@ffwll.ch>
28 /** @file gem_set_tiling_vs_blt.c
30 * Testcase: Check for proper synchronization of tiling changes vs. tiled gpu
33 * The blitter on gen3 and earlier needs properly set up fences. Which also
34 * means that for untiled blits we may not set up a fence before that blt has
37 * Current kernels have a bug there, but it's pretty hard to hit because you
39 * - a blt on an untiled object which is aligned correctly for tiling.
40 * - a set_tiling to switch that object to tiling
41 * - another blt without any intervening cpu access that uses this object.
43 * Testcase has been extended to also check tiled->untiled and tiled->tiled
44 * transitions (i.e. changing stride).
57 #include "ioctl_wrappers.h"
59 #include "intel_bufmgr.h"
60 #include "intel_batchbuffer.h"
61 #include "intel_chipset.h"
64 static drm_intel_bufmgr *bufmgr;
65 struct intel_batchbuffer *batch;
68 #define TEST_SIZE (1024*1024)
69 #define TEST_STRIDE (4*1024)
70 #define TEST_HEIGHT(stride) (TEST_SIZE/(stride))
71 #define TEST_WIDTH(stride) ((stride)/4)
73 uint32_t data[TEST_SIZE/4];
75 static void do_test(uint32_t tiling, unsigned stride,
76 uint32_t tiling_after, unsigned stride_after)
78 drm_intel_bo *busy_bo, *test_bo, *target_bo;
81 uint32_t test_bo_handle;
82 uint32_t blt_stride, blt_bits;
83 bool tiling_changed = false;
85 igt_info("filling ring .. ");
86 busy_bo = drm_intel_bo_alloc(bufmgr, "busy bo bo", 16*1024*1024, 4096);
88 for (i = 0; i < 250; i++) {
89 BLIT_COPY_BATCH_START(0);
90 OUT_BATCH((3 << 24) | /* 32 bits */
91 (0xcc << 16) | /* copy ROP */
93 OUT_BATCH(0 << 16 | 1024);
94 OUT_BATCH((2048) << 16 | (2048));
95 OUT_RELOC_FENCED(busy_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
96 OUT_BATCH(0 << 16 | 0);
98 OUT_RELOC_FENCED(busy_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
101 if (batch->gen >= 6) {
103 OUT_BATCH(XY_SETUP_CLIP_BLT_CMD);
109 intel_batchbuffer_flush(batch);
111 igt_info("playing tricks .. ");
112 /* first allocate the target so it gets out of the way of playing funky
114 target_bo = drm_intel_bo_alloc(bufmgr, "target bo", TEST_SIZE, 4096);
116 /* allocate buffer with parameters _after_ transition we want to check
117 * and touch it, so that it's properly aligned in the gtt. */
118 test_bo = drm_intel_bo_alloc(bufmgr, "tiled busy bo", TEST_SIZE, 4096);
119 test_bo_handle = test_bo->handle;
120 ret = drm_intel_bo_set_tiling(test_bo, &tiling_after, stride_after);
121 igt_assert(ret == 0);
122 drm_intel_gem_bo_map_gtt(test_bo);
123 ptr = test_bo->virtual;
126 drm_intel_gem_bo_unmap_gtt(test_bo);
128 drm_intel_bo_unreference(test_bo);
132 /* note we need a bo bigger than batches, otherwise the buffer reuse
133 * trick will fail. */
134 test_bo = drm_intel_bo_alloc(bufmgr, "busy bo", TEST_SIZE, 4096);
135 /* double check that the reuse trick worked */
136 igt_assert(test_bo_handle == test_bo->handle);
138 test_bo_handle = test_bo->handle;
139 /* ensure we have the right tiling before we start. */
140 ret = drm_intel_bo_set_tiling(test_bo, &tiling, stride);
141 igt_assert(ret == 0);
143 if (tiling == I915_TILING_NONE) {
144 drm_intel_bo_subdata(test_bo, 0, TEST_SIZE, data);
146 drm_intel_gem_bo_map_gtt(test_bo);
147 ptr = test_bo->virtual;
148 memcpy(ptr, data, TEST_SIZE);
150 drm_intel_gem_bo_unmap_gtt(test_bo);
155 if (intel_gen(devid) >= 4 && tiling != I915_TILING_NONE) {
157 blt_bits = XY_SRC_COPY_BLT_SRC_TILED;
160 BLIT_COPY_BATCH_START(blt_bits);
161 OUT_BATCH((3 << 24) | /* 32 bits */
162 (0xcc << 16) | /* copy ROP */
164 OUT_BATCH(0 << 16 | 0);
165 OUT_BATCH((TEST_HEIGHT(stride)) << 16 | (TEST_WIDTH(stride)));
166 OUT_RELOC_FENCED(target_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
167 OUT_BATCH(0 << 16 | 0);
168 OUT_BATCH(blt_stride);
169 OUT_RELOC_FENCED(test_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
171 intel_batchbuffer_flush(batch);
173 drm_intel_bo_unreference(test_bo);
175 test_bo = drm_intel_bo_alloc_for_render(bufmgr, "tiled busy bo", TEST_SIZE, 4096);
176 /* double check that the reuse trick worked */
177 igt_assert(test_bo_handle == test_bo->handle);
178 ret = drm_intel_bo_set_tiling(test_bo, &tiling_after, stride_after);
179 igt_assert(ret == 0);
181 /* Note: We don't care about gen4+ here because the blitter doesn't use
182 * fences there. So not setting tiling flags on the tiled buffer is ok.
184 BLIT_COPY_BATCH_START(0);
185 OUT_BATCH((3 << 24) | /* 32 bits */
186 (0xcc << 16) | /* copy ROP */
188 OUT_BATCH(0 << 16 | 0);
189 OUT_BATCH((1) << 16 | (1));
190 OUT_RELOC_FENCED(test_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
191 OUT_BATCH(0 << 16 | 0);
192 OUT_BATCH(stride_after);
193 OUT_RELOC_FENCED(test_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
195 intel_batchbuffer_flush(batch);
197 /* Now try to trick the kernel the kernel into changing up the fencing
200 igt_info("checking .. ");
201 memset(data, 0, TEST_SIZE);
202 drm_intel_bo_get_subdata(target_bo, 0, TEST_SIZE, data);
203 for (i = 0; i < TEST_SIZE/4; i++)
204 igt_assert(data[i] == i);
206 /* check whether tiling on the test_bo actually changed. */
207 drm_intel_gem_bo_map_gtt(test_bo);
208 ptr = test_bo->virtual;
209 for (i = 0; i < TEST_SIZE/4; i++)
210 if (ptr[i] != data[i])
211 tiling_changed = true;
213 drm_intel_gem_bo_unmap_gtt(test_bo);
214 igt_assert(tiling_changed);
216 drm_intel_bo_unreference(test_bo);
217 drm_intel_bo_unreference(target_bo);
218 drm_intel_bo_unreference(busy_bo);
227 uint32_t tiling, tiling_after;
229 igt_skip_on_simulation();
232 for (i = 0; i < 1024*256; i++)
237 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
238 drm_intel_bufmgr_gem_enable_reuse(bufmgr);
239 devid = intel_get_drm_devid(fd);
240 batch = intel_batchbuffer_alloc(bufmgr, devid);
243 igt_subtest("untiled-to-tiled") {
244 tiling = I915_TILING_NONE;
245 tiling_after = I915_TILING_X;
246 do_test(tiling, TEST_STRIDE, tiling_after, TEST_STRIDE);
247 igt_assert(tiling == I915_TILING_NONE);
248 igt_assert(tiling_after == I915_TILING_X);
251 igt_subtest("tiled-to-untiled") {
252 tiling = I915_TILING_X;
253 tiling_after = I915_TILING_NONE;
254 do_test(tiling, TEST_STRIDE, tiling_after, TEST_STRIDE);
255 igt_assert(tiling == I915_TILING_X);
256 igt_assert(tiling_after == I915_TILING_NONE);
259 igt_subtest("tiled-to-tiled") {
260 tiling = I915_TILING_X;
261 tiling_after = I915_TILING_X;
262 do_test(tiling, TEST_STRIDE/2, tiling_after, TEST_STRIDE);
263 igt_assert(tiling == I915_TILING_X);
264 igt_assert(tiling_after == I915_TILING_X);