2 * Copyright © 2012 Intel Corporation
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11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Vetter <daniel.vetter@ffwll.ch>
28 /** @file gem_set_tiling_vs_blt.c
30 * Testcase: Check for proper synchronization of tiling changes vs. tiled gpu
33 * The blitter on gen3 and earlier needs properly set up fences. Which also
34 * means that for untiled blits we may not set up a fence before that blt has
37 * Current kernels have a bug there, but it's pretty hard to hit because you
39 * - a blt on an untiled object which is aligned correctly for tiling.
40 * - a set_tiling to switch that object to tiling
41 * - another blt without any intervening cpu access that uses this object.
43 * Testcase has been extended to also check tiled->untiled and tiled->tiled
44 * transitions (i.e. changing stride).
57 #include "ioctl_wrappers.h"
59 #include "intel_bufmgr.h"
60 #include "intel_batchbuffer.h"
61 #include "intel_chipset.h"
64 static drm_intel_bufmgr *bufmgr;
65 struct intel_batchbuffer *batch;
68 #define TEST_SIZE (1024*1024)
69 #define TEST_STRIDE (4*1024)
70 #define TEST_HEIGHT(stride) (TEST_SIZE/(stride))
71 #define TEST_WIDTH(stride) ((stride)/4)
73 uint32_t data[TEST_SIZE/4];
75 static void do_test(uint32_t tiling, unsigned stride,
76 uint32_t tiling_after, unsigned stride_after)
78 drm_intel_bo *busy_bo, *test_bo, *target_bo;
81 uint32_t test_bo_handle;
82 uint32_t blt_stride, blt_bits;
83 bool tiling_changed = false;
85 igt_info("filling ring .. ");
86 busy_bo = drm_intel_bo_alloc(bufmgr, "busy bo bo", 16*1024*1024, 4096);
88 for (i = 0; i < 250; i++) {
89 BLIT_COPY_BATCH_START(devid, 0);
90 OUT_BATCH((3 << 24) | /* 32 bits */
91 (0xcc << 16) | /* copy ROP */
93 OUT_BATCH(0 << 16 | 1024);
94 OUT_BATCH((2048) << 16 | (2048));
95 OUT_RELOC_FENCED(busy_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
96 BLIT_RELOC_UDW(devid);
97 OUT_BATCH(0 << 16 | 0);
99 OUT_RELOC_FENCED(busy_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
100 BLIT_RELOC_UDW(devid);
103 if (IS_GEN6(devid) || IS_GEN7(devid)) {
105 OUT_BATCH(XY_SETUP_CLIP_BLT_CMD);
111 intel_batchbuffer_flush(batch);
113 igt_info("playing tricks .. ");
114 /* first allocate the target so it gets out of the way of playing funky
116 target_bo = drm_intel_bo_alloc(bufmgr, "target bo", TEST_SIZE, 4096);
118 /* allocate buffer with parameters _after_ transition we want to check
119 * and touch it, so that it's properly aligned in the gtt. */
120 test_bo = drm_intel_bo_alloc(bufmgr, "tiled busy bo", TEST_SIZE, 4096);
121 test_bo_handle = test_bo->handle;
122 ret = drm_intel_bo_set_tiling(test_bo, &tiling_after, stride_after);
123 igt_assert(ret == 0);
124 drm_intel_gem_bo_map_gtt(test_bo);
125 ptr = test_bo->virtual;
128 drm_intel_gem_bo_unmap_gtt(test_bo);
130 drm_intel_bo_unreference(test_bo);
134 /* note we need a bo bigger than batches, otherwise the buffer reuse
135 * trick will fail. */
136 test_bo = drm_intel_bo_alloc(bufmgr, "busy bo", TEST_SIZE, 4096);
137 /* double check that the reuse trick worked */
138 igt_assert(test_bo_handle == test_bo->handle);
140 test_bo_handle = test_bo->handle;
141 /* ensure we have the right tiling before we start. */
142 ret = drm_intel_bo_set_tiling(test_bo, &tiling, stride);
143 igt_assert(ret == 0);
145 if (tiling == I915_TILING_NONE) {
146 drm_intel_bo_subdata(test_bo, 0, TEST_SIZE, data);
148 drm_intel_gem_bo_map_gtt(test_bo);
149 ptr = test_bo->virtual;
150 memcpy(ptr, data, TEST_SIZE);
152 drm_intel_gem_bo_unmap_gtt(test_bo);
157 if (intel_gen(devid) >= 4 && tiling != I915_TILING_NONE) {
159 blt_bits = XY_SRC_COPY_BLT_SRC_TILED;
162 BLIT_COPY_BATCH_START(devid, blt_bits);
163 OUT_BATCH((3 << 24) | /* 32 bits */
164 (0xcc << 16) | /* copy ROP */
166 OUT_BATCH(0 << 16 | 0);
167 OUT_BATCH((TEST_HEIGHT(stride)) << 16 | (TEST_WIDTH(stride)));
168 OUT_RELOC_FENCED(target_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
169 BLIT_RELOC_UDW(devid);
170 OUT_BATCH(0 << 16 | 0);
171 OUT_BATCH(blt_stride);
172 OUT_RELOC_FENCED(test_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
173 BLIT_RELOC_UDW(devid);
175 intel_batchbuffer_flush(batch);
177 drm_intel_bo_unreference(test_bo);
179 test_bo = drm_intel_bo_alloc_for_render(bufmgr, "tiled busy bo", TEST_SIZE, 4096);
180 /* double check that the reuse trick worked */
181 igt_assert(test_bo_handle == test_bo->handle);
182 ret = drm_intel_bo_set_tiling(test_bo, &tiling_after, stride_after);
183 igt_assert(ret == 0);
185 /* Note: We don't care about gen4+ here because the blitter doesn't use
186 * fences there. So not setting tiling flags on the tiled buffer is ok.
188 BLIT_COPY_BATCH_START(devid, 0);
189 OUT_BATCH((3 << 24) | /* 32 bits */
190 (0xcc << 16) | /* copy ROP */
192 OUT_BATCH(0 << 16 | 0);
193 OUT_BATCH((1) << 16 | (1));
194 OUT_RELOC_FENCED(test_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
195 BLIT_RELOC_UDW(devid);
196 OUT_BATCH(0 << 16 | 0);
197 OUT_BATCH(stride_after);
198 OUT_RELOC_FENCED(test_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
199 BLIT_RELOC_UDW(devid);
201 intel_batchbuffer_flush(batch);
203 /* Now try to trick the kernel the kernel into changing up the fencing
206 igt_info("checking .. ");
207 memset(data, 0, TEST_SIZE);
208 drm_intel_bo_get_subdata(target_bo, 0, TEST_SIZE, data);
209 for (i = 0; i < TEST_SIZE/4; i++)
210 igt_assert(data[i] == i);
212 /* check whether tiling on the test_bo actually changed. */
213 drm_intel_gem_bo_map_gtt(test_bo);
214 ptr = test_bo->virtual;
215 for (i = 0; i < TEST_SIZE/4; i++)
216 if (ptr[i] != data[i])
217 tiling_changed = true;
219 drm_intel_gem_bo_unmap_gtt(test_bo);
220 igt_assert(tiling_changed);
222 drm_intel_bo_unreference(test_bo);
223 drm_intel_bo_unreference(target_bo);
224 drm_intel_bo_unreference(busy_bo);
233 uint32_t tiling, tiling_after;
235 igt_skip_on_simulation();
238 for (i = 0; i < 1024*256; i++)
243 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
244 drm_intel_bufmgr_gem_enable_reuse(bufmgr);
245 devid = intel_get_drm_devid(fd);
246 batch = intel_batchbuffer_alloc(bufmgr, devid);
249 igt_subtest("untiled-to-tiled") {
250 tiling = I915_TILING_NONE;
251 tiling_after = I915_TILING_X;
252 do_test(tiling, TEST_STRIDE, tiling_after, TEST_STRIDE);
253 igt_assert(tiling == I915_TILING_NONE);
254 igt_assert(tiling_after == I915_TILING_X);
257 igt_subtest("tiled-to-untiled") {
258 tiling = I915_TILING_X;
259 tiling_after = I915_TILING_NONE;
260 do_test(tiling, TEST_STRIDE, tiling_after, TEST_STRIDE);
261 igt_assert(tiling == I915_TILING_X);
262 igt_assert(tiling_after == I915_TILING_NONE);
265 igt_subtest("tiled-to-tiled") {
266 tiling = I915_TILING_X;
267 tiling_after = I915_TILING_X;
268 do_test(tiling, TEST_STRIDE/2, tiling_after, TEST_STRIDE);
269 igt_assert(tiling == I915_TILING_X);
270 igt_assert(tiling_after == I915_TILING_X);