2 * Copyright (c) 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Mika Kuoppala <mika.kuoppala@intel.com>
29 * This test runs blitcopy -> rendercopy with multiple buffers over wrap
38 #include <sys/types.h>
45 #include "ioctl_wrappers.h"
49 #include "intel_bufmgr.h"
50 #include "intel_batchbuffer.h"
52 #include "intel_chipset.h"
55 static int card_index = 0;
56 static uint32_t last_seqno = 0;
58 static struct intel_batchbuffer *batch_blt;
59 static struct intel_batchbuffer *batch_3d;
61 struct option_struct {
71 static struct option_struct options;
73 static void init_buffer(drm_intel_bufmgr *bufmgr,
76 int width, int height)
78 /* buf->bo = drm_intel_bo_alloc(bufmgr, "", size, 4096); */
80 buf->size = width * height * 4;
82 buf->tiling = I915_TILING_NONE;
83 buf->num_tiles = width * height * 4;
84 buf->stride = width * 4;
88 set_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
90 int size = width * height;
93 drm_intel_gem_bo_start_gtt_access(bo, true);
100 cmp_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
102 int size = width * height;
105 drm_intel_gem_bo_start_gtt_access(bo, false);
108 igt_assert_f(*vaddr++ == val,
109 "%d: 0x%x differs from assumed 0x%x\n"
110 "seqno_before_test 0x%x, "
111 " approximated seqno on test fail 0x%x\n",
112 width * height - size, *vaddr-1, val,
113 last_seqno, last_seqno + val * 2);
117 static drm_intel_bo *
118 create_bo(drm_intel_bufmgr *bufmgr, uint32_t val, int width, int height)
122 bo = drm_intel_bo_alloc(bufmgr, "bo", width * height * 4, 0);
125 /* gtt map doesn't have a write parameter, so just keep the mapping
126 * around (to avoid the set_domain with the gtt write domain set) and
127 * manually tell the kernel when we start access the gtt. */
128 drm_intel_gem_bo_map_gtt(bo);
130 set_bo(bo, val, width, height);
135 static void release_bo(drm_intel_bo *bo)
137 drm_intel_gem_bo_unmap_gtt(bo);
138 drm_intel_bo_unreference(bo);
141 static void render_copyfunc(struct igt_buf *src,
146 const int src_x = 0, src_y = 0, dst_x = 0, dst_y = 0;
147 igt_render_copyfunc_t rendercopy = igt_get_render_copyfunc(devid);
148 static int warned = 0;
151 rendercopy(batch_3d, NULL,
155 intel_batchbuffer_flush(batch_3d);
158 igt_info("No render copy found for this gen, ""test is shallow!\n");
163 intel_copy_bo(batch_blt, dst->bo, src->bo, width*height*4);
164 intel_batchbuffer_flush(batch_blt);
168 static void exchange_uint(void *array, unsigned i, unsigned j)
170 unsigned *i_arr = array;
178 static void run_sync_test(int num_buffers, bool verify)
180 drm_intel_bufmgr *bufmgr;
182 drm_intel_bo **src, **dst1, **dst2;
183 int width = 128, height = 128;
186 unsigned int *p_dst1, *p_dst2;
187 struct igt_buf *s_src, *s_dst;
192 gem_quiescent_gpu(fd);
194 devid = intel_get_drm_devid(fd);
196 max = gem_aperture_size (fd) / (1024 * 1024) / 2;
197 if (num_buffers > max)
200 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
201 drm_intel_bufmgr_gem_enable_reuse(bufmgr);
202 batch_blt = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
203 igt_assert(batch_blt);
204 batch_3d = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
205 igt_assert(batch_3d);
207 src = malloc(num_buffers * sizeof(*src));
210 dst1 = malloc(num_buffers * sizeof(*dst1));
213 dst2 = malloc(num_buffers * sizeof(*dst2));
216 s_src = malloc(num_buffers * sizeof(*s_src));
219 s_dst = malloc(num_buffers * sizeof(*s_dst));
222 p_dst1 = malloc(num_buffers * sizeof(unsigned int));
225 p_dst2 = malloc(num_buffers * sizeof(unsigned int));
228 for (i = 0; i < num_buffers; i++) {
229 p_dst1[i] = p_dst2[i] = i;
230 src[i] = create_bo(bufmgr, i, width, height);
232 dst1[i] = create_bo(bufmgr, ~i, width, height);
234 dst2[i] = create_bo(bufmgr, ~i, width, height);
236 init_buffer(bufmgr, &s_src[i], src[i], width, height);
237 init_buffer(bufmgr, &s_dst[i], dst1[i], width, height);
240 igt_permute_array(p_dst1, num_buffers, exchange_uint);
241 igt_permute_array(p_dst2, num_buffers, exchange_uint);
243 for (i = 0; i < num_buffers; i++)
244 render_copyfunc(&s_src[i], &s_dst[p_dst1[i]], width, height);
246 /* Only sync between buffers if this is actual test run and
247 * not a seqno filler */
249 for (i = 0; i < num_buffers; i++)
250 intel_copy_bo(batch_blt, dst2[p_dst2[i]], dst1[p_dst1[i]],
253 for (i = 0; i < num_buffers; i++) {
254 cmp_bo(dst2[p_dst2[i]], i, width, height);
258 for (i = 0; i < num_buffers; i++) {
264 intel_batchbuffer_free(batch_3d);
265 intel_batchbuffer_free(batch_blt);
266 drm_intel_bufmgr_destroy(bufmgr);
276 gem_quiescent_gpu(fd);
281 static const char *dfs_base = "/sys/kernel/debug/dri";
282 static const char *dfs_entry = "i915_next_seqno";
284 static int dfs_open(int mode)
286 char fname[FILENAME_MAX];
289 snprintf(fname, FILENAME_MAX, "%s/%i/%s",
290 dfs_base, card_index, dfs_entry);
292 fh = open(fname, mode);
293 igt_require(fh >= 0);
298 static int __read_seqno(uint32_t *seqno)
304 unsigned long int tmp;
306 fh = dfs_open(O_RDONLY);
308 r = read(fh, buf, sizeof(buf) - 1);
317 p = strstr(buf, "0x");
322 tmp = strtoul(p, NULL, 0);
323 if (tmp == ULONG_MAX && errno) {
330 igt_debug("next_seqno: 0x%x\n", *seqno);
335 static int read_seqno(void)
341 r = __read_seqno(&seqno);
344 if (last_seqno > seqno)
352 static int write_seqno(uint32_t seqno)
359 if (options.dontwrap)
362 fh = dfs_open(O_RDWR);
363 igt_assert(snprintf(buf, sizeof(buf), "0x%x", seqno) > 0);
365 r = write(fh, buf, strnlen(buf, sizeof(buf)));
370 igt_assert(r == strnlen(buf, sizeof(buf)));
374 igt_debug("next_seqno set to: 0x%x\n", seqno);
376 r = __read_seqno(&rb);
381 igt_info("seqno readback differs rb:0x%x vs w:0x%x\n", rb, seqno);
388 static uint32_t calc_prewrap_val(void)
390 const int pval = options.prewrap_space;
392 if (options.random == 0)
398 return (random() % pval);
401 static void run_test(void)
403 run_sync_test(options.buffers, true);
406 static void preset_run_once(void)
408 igt_assert(write_seqno(1) == 0);
411 igt_assert(write_seqno(0x7fffffff) == 0);
414 igt_assert(write_seqno(0xffffffff) == 0);
417 igt_assert(write_seqno(0xfffffff0) == 0);
421 static void random_run_once(void)
426 val = random() % UINT32_MAX;
427 if (RAND_MAX < UINT32_MAX)
431 igt_assert(write_seqno(val) == 0);
435 static void wrap_run_once(void)
437 const uint32_t pw_val = calc_prewrap_val();
439 igt_assert(write_seqno(UINT32_MAX - pw_val) == 0);
445 static void background_run_once(void)
447 const uint32_t pw_val = calc_prewrap_val();
449 igt_assert(write_seqno(UINT32_MAX - pw_val) == 0);
455 static void print_usage(const char *s)
457 igt_info("%s: [OPTION]...\n", s);
458 igt_info(" where options are:\n");
459 igt_info(" -b --background run in background inducing wraps\n");
460 igt_info(" -n --rounds=num run num times across wrap boundary, 0 == forever\n");
461 igt_info(" -t --timeout=sec set timeout to wait for testrun to sec seconds\n");
462 igt_info(" -d --dontwrap don't wrap just run the test\n");
463 igt_info(" -p --prewrap=n set seqno to WRAP - n for each testrun\n");
464 igt_info(" -r --norandom dont randomize prewrap space\n");
465 igt_info(" -i --buffers number of buffers to copy\n");
469 static void parse_options(int argc, char **argv)
472 int option_index = 0;
473 static struct option long_options[] = {
474 {"rounds", required_argument, 0, 'n'},
475 {"background", no_argument, 0, 'b'},
476 {"timeout", required_argument, 0, 't'},
477 {"dontwrap", no_argument, 0, 'd'},
478 {"prewrap", required_argument, 0, 'p'},
479 {"norandom", no_argument, 0, 'r'},
480 {"buffers", required_argument, 0, 'i'},
483 options.rounds = SLOW_QUICK(50, 2);
484 options.background = 0;
485 options.dontwrap = 0;
486 options.timeout = 20;
488 options.prewrap_space = 21;
489 options.buffers = 10;
491 while((c = getopt_long(argc, argv, "n:bvt:dp:ri:",
492 long_options, &option_index)) != -1) {
495 options.background = 1;
496 igt_info("running in background inducing wraps\n");
499 options.dontwrap = 1;
500 igt_info("won't wrap after testruns\n");
503 options.rounds = atoi(optarg);
504 igt_info("running %d rounds\n", options.rounds);
507 options.buffers = atoi(optarg);
508 igt_info("buffers %d\n", options.buffers);
511 options.timeout = atoi(optarg);
512 if (options.timeout == 0)
513 options.timeout = 10;
514 igt_info("setting timeout to %d seconds\n", options.timeout);
520 options.prewrap_space = atoi(optarg);
521 igt_info("prewrap set to %d (0x%x)\n", options.prewrap_space, UINT32_MAX - options.prewrap_space);
524 igt_info("unkown command options\n");
525 print_usage(argv[0]);
531 igt_info("unkown command options\n");
532 print_usage(argv[0]);
536 int main(int argc, char **argv)
543 parse_options(argc, argv);
545 card_index = drm_get_card();
549 while(options.rounds == 0 || wcount < options.rounds) {
550 if (options.background) {
551 background_run_once();
560 igt_debug("%s done: %d\n",
561 options.dontwrap ? "tests" : "wraps", wcount);
564 if (options.rounds == wcount) {
565 igt_debug("done %d wraps successfully\n", wcount);