2 * Copyright (c) 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Mika Kuoppala <mika.kuoppala@intel.com>
29 * This test runs blitcopy -> rendercopy with multiple buffers over wrap
38 #include <sys/types.h>
44 #include "ioctl_wrappers.h"
48 #include "intel_bufmgr.h"
49 #include "intel_batchbuffer.h"
51 #include "intel_chipset.h"
54 static int card_index = 0;
55 static uint32_t last_seqno = 0;
57 static struct intel_batchbuffer *batch_blt;
58 static struct intel_batchbuffer *batch_3d;
60 struct option_struct {
70 static struct option_struct options;
72 static void init_buffer(drm_intel_bufmgr *bufmgr,
75 int width, int height)
77 /* buf->bo = drm_intel_bo_alloc(bufmgr, "", size, 4096); */
79 buf->size = width * height * 4;
81 buf->tiling = I915_TILING_NONE;
82 buf->num_tiles = width * height * 4;
83 buf->stride = width * 4;
87 set_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
89 int size = width * height;
92 drm_intel_gem_bo_start_gtt_access(bo, true);
99 cmp_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
101 int size = width * height;
104 drm_intel_gem_bo_start_gtt_access(bo, false);
107 igt_assert_f(*vaddr++ == val,
108 "%d: 0x%x differs from assumed 0x%x\n"
109 "seqno_before_test 0x%x, "
110 " approximated seqno on test fail 0x%x\n",
111 width * height - size, *vaddr-1, val,
112 last_seqno, last_seqno + val * 2);
116 static drm_intel_bo *
117 create_bo(drm_intel_bufmgr *bufmgr, uint32_t val, int width, int height)
121 bo = drm_intel_bo_alloc(bufmgr, "bo", width * height * 4, 0);
124 /* gtt map doesn't have a write parameter, so just keep the mapping
125 * around (to avoid the set_domain with the gtt write domain set) and
126 * manually tell the kernel when we start access the gtt. */
127 drm_intel_gem_bo_map_gtt(bo);
129 set_bo(bo, val, width, height);
134 static void release_bo(drm_intel_bo *bo)
136 drm_intel_gem_bo_unmap_gtt(bo);
137 drm_intel_bo_unreference(bo);
140 static void render_copyfunc(struct igt_buf *src,
145 const int src_x = 0, src_y = 0, dst_x = 0, dst_y = 0;
146 igt_render_copyfunc_t rendercopy = igt_get_render_copyfunc(devid);
147 static int warned = 0;
150 rendercopy(batch_3d, NULL,
154 intel_batchbuffer_flush(batch_3d);
157 igt_info("No render copy found for this gen, ""test is shallow!\n");
162 intel_copy_bo(batch_blt, dst->bo, src->bo, width*height*4);
163 intel_batchbuffer_flush(batch_blt);
167 static void exchange_uint(void *array, unsigned i, unsigned j)
169 unsigned *i_arr = array;
177 static void run_sync_test(int num_buffers, bool verify)
179 drm_intel_bufmgr *bufmgr;
181 drm_intel_bo **src, **dst1, **dst2;
182 int width = 128, height = 128;
185 unsigned int *p_dst1, *p_dst2;
186 struct igt_buf *s_src, *s_dst;
191 gem_quiescent_gpu(fd);
193 devid = intel_get_drm_devid(fd);
195 max = gem_aperture_size (fd) / (1024 * 1024) / 2;
196 if (num_buffers > max)
199 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
200 drm_intel_bufmgr_gem_enable_reuse(bufmgr);
201 batch_blt = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
202 igt_assert(batch_blt);
203 batch_3d = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
204 igt_assert(batch_3d);
206 src = malloc(num_buffers * sizeof(*src));
209 dst1 = malloc(num_buffers * sizeof(*dst1));
212 dst2 = malloc(num_buffers * sizeof(*dst2));
215 s_src = malloc(num_buffers * sizeof(*s_src));
218 s_dst = malloc(num_buffers * sizeof(*s_dst));
221 p_dst1 = malloc(num_buffers * sizeof(unsigned int));
224 p_dst2 = malloc(num_buffers * sizeof(unsigned int));
227 for (i = 0; i < num_buffers; i++) {
228 p_dst1[i] = p_dst2[i] = i;
229 src[i] = create_bo(bufmgr, i, width, height);
231 dst1[i] = create_bo(bufmgr, ~i, width, height);
233 dst2[i] = create_bo(bufmgr, ~i, width, height);
235 init_buffer(bufmgr, &s_src[i], src[i], width, height);
236 init_buffer(bufmgr, &s_dst[i], dst1[i], width, height);
239 igt_permute_array(p_dst1, num_buffers, exchange_uint);
240 igt_permute_array(p_dst2, num_buffers, exchange_uint);
242 for (i = 0; i < num_buffers; i++)
243 render_copyfunc(&s_src[i], &s_dst[p_dst1[i]], width, height);
245 /* Only sync between buffers if this is actual test run and
246 * not a seqno filler */
248 for (i = 0; i < num_buffers; i++)
249 intel_copy_bo(batch_blt, dst2[p_dst2[i]], dst1[p_dst1[i]],
252 for (i = 0; i < num_buffers; i++) {
253 cmp_bo(dst2[p_dst2[i]], i, width, height);
257 for (i = 0; i < num_buffers; i++) {
263 intel_batchbuffer_free(batch_3d);
264 intel_batchbuffer_free(batch_blt);
265 drm_intel_bufmgr_destroy(bufmgr);
275 gem_quiescent_gpu(fd);
280 static const char *dfs_base = "/sys/kernel/debug/dri";
281 static const char *dfs_entry = "i915_next_seqno";
283 static int dfs_open(int mode)
285 char fname[FILENAME_MAX];
288 snprintf(fname, FILENAME_MAX, "%s/%i/%s",
289 dfs_base, card_index, dfs_entry);
291 fh = open(fname, mode);
292 igt_require(fh >= 0);
297 static int __read_seqno(uint32_t *seqno)
303 unsigned long int tmp;
305 fh = dfs_open(O_RDONLY);
307 r = read(fh, buf, sizeof(buf) - 1);
316 p = strstr(buf, "0x");
321 tmp = strtoul(p, NULL, 0);
322 if (tmp == ULONG_MAX && errno) {
329 igt_debug("next_seqno: 0x%x\n", *seqno);
334 static int read_seqno(void)
340 r = __read_seqno(&seqno);
343 if (last_seqno > seqno)
351 static int write_seqno(uint32_t seqno)
358 if (options.dontwrap)
361 fh = dfs_open(O_RDWR);
362 igt_assert(snprintf(buf, sizeof(buf), "0x%x", seqno) > 0);
364 r = write(fh, buf, strnlen(buf, sizeof(buf)));
369 igt_assert(r == strnlen(buf, sizeof(buf)));
373 igt_debug("next_seqno set to: 0x%x\n", seqno);
375 r = __read_seqno(&rb);
380 igt_info("seqno readback differs rb:0x%x vs w:0x%x\n", rb, seqno);
387 static uint32_t calc_prewrap_val(void)
389 const int pval = options.prewrap_space;
391 if (options.random == 0)
397 return (random() % pval);
400 static void run_test(void)
402 run_sync_test(options.buffers, true);
405 static void preset_run_once(void)
407 igt_assert(write_seqno(1) == 0);
410 igt_assert(write_seqno(0x7fffffff) == 0);
413 igt_assert(write_seqno(0xffffffff) == 0);
416 igt_assert(write_seqno(0xfffffff0) == 0);
420 static void random_run_once(void)
425 val = random() % UINT32_MAX;
426 if (RAND_MAX < UINT32_MAX)
430 igt_assert(write_seqno(val) == 0);
434 static void wrap_run_once(void)
436 const uint32_t pw_val = calc_prewrap_val();
438 igt_assert(write_seqno(UINT32_MAX - pw_val) == 0);
444 static void background_run_once(void)
446 const uint32_t pw_val = calc_prewrap_val();
448 igt_assert(write_seqno(UINT32_MAX - pw_val) == 0);
454 static int parse_options(int opt, int opt_index)
458 options.background = 1;
459 igt_info("running in background inducing wraps\n");
462 options.dontwrap = 1;
463 igt_info("won't wrap after testruns\n");
466 options.rounds = atoi(optarg);
467 igt_info("running %d rounds\n", options.rounds);
470 options.buffers = atoi(optarg);
471 igt_info("buffers %d\n", options.buffers);
474 options.timeout = atoi(optarg);
475 if (options.timeout == 0)
476 options.timeout = 10;
477 igt_info("setting timeout to %d seconds\n", options.timeout);
483 options.prewrap_space = atoi(optarg);
484 igt_info("prewrap set to %d (0x%x)\n", options.prewrap_space, UINT32_MAX - options.prewrap_space);
491 int main(int argc, char **argv)
496 static struct option long_options[] = {
497 {"rounds", required_argument, 0, 'n'},
498 {"background", no_argument, 0, 'b'},
499 {"timeout", required_argument, 0, 't'},
500 {"dontwrap", no_argument, 0, 'd'},
501 {"prewrap", required_argument, 0, 'p'},
502 {"norandom", no_argument, 0, 'r'},
503 {"buffers", required_argument, 0, 'i'},
508 " -b --background run in background inducing wraps\n"
509 " -n --rounds=num run num times across wrap boundary, 0 == forever\n"
510 " -t --timeout=sec set timeout to wait for testrun to sec seconds\n"
511 " -d --dontwrap don't wrap just run the test\n"
512 " -p --prewrap=n set seqno to WRAP - n for each testrun\n"
513 " -r --norandom dont randomize prewrap space\n"
514 " -i --buffers number of buffers to copy\n";
516 options.rounds = SLOW_QUICK(50, 2);
517 options.background = 0;
518 options.dontwrap = 0;
519 options.timeout = 20;
521 options.prewrap_space = 21;
522 options.buffers = 10;
524 igt_simple_init_parse_opts(argc, argv, "n:bvt:dp:ri:", long_options,
525 help, parse_options);
527 card_index = drm_get_card();
531 while(options.rounds == 0 || wcount < options.rounds) {
532 if (options.background) {
533 background_run_once();
542 igt_debug("%s done: %d\n",
543 options.dontwrap ? "tests" : "wraps", wcount);
546 if (options.rounds == wcount) {
547 igt_debug("done %d wraps successfully\n", wcount);