2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Vetter <daniel.vetter@ffwll.ch> (based on gem_storedw_*.c)
37 #include "ioctl_wrappers.h"
39 #include "intel_bufmgr.h"
40 #include "intel_batchbuffer.h"
43 #include "intel_chipset.h"
45 static drm_intel_bufmgr *bufmgr;
46 struct intel_batchbuffer *batch;
47 static drm_intel_bo *target_buffer;
50 * Testcase: Basic check of ring<->ring sync using a dummy reloc
52 * Extremely efficient at catching missed irqs with semaphores=0 ...
55 #define MI_COND_BATCH_BUFFER_END (0x36<<23 | 1)
56 #define MI_DO_COMPARE (1<<21)
59 store_dword_loop(int fd)
62 int num_rings = gem_get_num_rings(fd);
66 for (i = 0; i < SLOW_QUICK(0x100000, 10); i++) {
67 int ring = random() % num_rings + 1;
69 if (ring == I915_EXEC_RENDER) {
71 OUT_BATCH(MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE);
72 OUT_BATCH(0xffffffff); /* compare dword */
73 OUT_RELOC(target_buffer, I915_GEM_DOMAIN_RENDER,
74 I915_GEM_DOMAIN_RENDER, 0);
79 OUT_BATCH(MI_FLUSH_DW | 1);
80 OUT_BATCH(0); /* reserved */
81 OUT_RELOC(target_buffer, I915_GEM_DOMAIN_RENDER,
82 I915_GEM_DOMAIN_RENDER, 0);
83 OUT_BATCH(MI_NOOP | (1<<22) | (0xf));
86 intel_batchbuffer_flush_on_ring(batch, ring);
89 drm_intel_bo_map(target_buffer, 0);
90 // map to force waiting on rendering
91 drm_intel_bo_unmap(target_buffer);
100 devid = intel_get_drm_devid(fd);
101 gem_require_ring(fd, I915_EXEC_BLT);
104 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
106 drm_intel_bufmgr_gem_enable_reuse(bufmgr);
108 batch = intel_batchbuffer_alloc(bufmgr, devid);
111 target_buffer = drm_intel_bo_alloc(bufmgr, "target bo", 4096, 4096);
112 igt_assert(target_buffer);
114 store_dword_loop(fd);
116 drm_intel_bo_unreference(target_buffer);
117 intel_batchbuffer_free(batch);
118 drm_intel_bufmgr_destroy(bufmgr);