2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
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11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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24 * Damien Lespiau <damien.lespiau@intel.com>
28 * The goal of this test is to ensure that we respect inter ring dependencies
30 * For each pair of rings R1, R2 where we have copy support (i.e. blt,
31 * rendercpy and mediafill) do:
32 * - Throw a busy load onto R1. gem_concurrent_blt just uses lots of buffers
34 * - Fill three buffers A, B, C with unique data.
35 * - Copy A to B on ring R1
37 * Then come the three different variants.
38 * - Copy B to C on ring R2, check that C now contains what A originally
39 * contained. This is the write->read hazard. gem_concurrent_blt calls this
41 * - Copy C to A on ring R2, check that B now contains what A originally
42 * contained. This is the read->write hazard, gem_concurrent_blt calls it
44 * - Copy C to B on ring R2 and check that B contains what C originally
45 * contained. This is the write/write hazard. gem_concurrent_blt doesn't
46 * have that since for the cpu case it's too boring.
53 #include "ioctl_wrappers.h"
55 #include "intel_batchbuffer.h"
56 #include "intel_chipset.h"
64 drm_intel_bufmgr *bufmgr;
65 struct intel_batchbuffer *batch;
67 /* number of buffers to keep the ring busy for a while */
68 unsigned int n_buffers_load;
70 uint32_t linear[WIDTH * HEIGHT];
73 igt_render_copyfunc_t copy;
96 static const char *ring_name(enum ring ring)
98 const char *names[] = {
106 static drm_intel_bo *bo_create(data_t *data, int width, int height, int val)
111 bo = drm_intel_bo_alloc(data->bufmgr, "", 4 * width * height, 4096);
114 for (i = 0; i < width * height; i++)
115 data->linear[i] = val;
116 gem_write(data->drm_fd, bo->handle, 0, data->linear,
117 sizeof(data->linear));
122 static void bo_check(data_t *data, drm_intel_bo *bo, uint32_t val)
126 gem_read(data->drm_fd, bo->handle, 0,
127 data->linear, sizeof(data->linear));
128 for (i = 0; i < WIDTH * HEIGHT; i++)
129 igt_assert_eq_u32(data->linear[i], val);
132 static void scratch_buf_init_from_bo(struct igt_buf *buf, drm_intel_bo *bo)
135 buf->stride = 4 * WIDTH;
136 buf->tiling = I915_TILING_NONE;
137 buf->size = 4 * WIDTH * HEIGHT;
140 static void scratch_buf_init(data_t *data, struct igt_buf *buf,
141 int width, int height, uint32_t color)
145 bo = bo_create(data, width, height, color);
146 scratch_buf_init_from_bo(buf, bo);
150 * Provide a few ring specific vfuncs for run_test().
152 * busy() Queue a n_buffers_load workloads onto the ring to keep it busy
153 * busy_fini() Clean up after busy
154 * copy() Copy one BO to another
161 static void render_busy(data_t *data)
166 array_size = data->n_buffers_load * sizeof(struct igt_buf);
167 data->render.srcs = malloc(array_size);
168 data->render.dsts = malloc(array_size);
170 for (i = 0; i < data->n_buffers_load; i++) {
171 scratch_buf_init(data, &data->render.srcs[i], WIDTH, HEIGHT,
173 scratch_buf_init(data, &data->render.dsts[i], WIDTH, HEIGHT,
177 for (i = 0; i < data->n_buffers_load; i++) {
178 data->render.copy(data->batch,
180 &data->render.srcs[i],
181 0, 0, /* src_x, src_y */
183 &data->render.dsts[i],
184 0, 0 /* dst_x, dst_y */);
188 static void render_busy_fini(data_t *data)
192 for (i = 0; i < data->n_buffers_load; i++) {
193 drm_intel_bo_unreference(data->render.srcs[i].bo);
194 drm_intel_bo_unreference(data->render.dsts[i].bo);
197 free(data->render.srcs);
198 free(data->render.dsts);
199 data->render.srcs = NULL;
200 data->render.dsts = NULL;
203 static void render_copy(data_t *data, drm_intel_bo *src, drm_intel_bo *dst)
205 struct igt_buf src_buf, dst_buf;
207 scratch_buf_init_from_bo(&src_buf, src);
208 scratch_buf_init_from_bo(&dst_buf, dst);
210 data->render.copy(data->batch,
213 0, 0, /* src_x, src_y */
216 0, 0 /* dst_x, dst_y */);
223 static void blitter_busy(data_t *data)
228 array_size = data->n_buffers_load * sizeof(drm_intel_bo *);
229 data->blitter.srcs = malloc(array_size);
230 data->blitter.dsts = malloc(array_size);
232 for (i = 0; i < data->n_buffers_load; i++) {
233 data->blitter.srcs[i] = bo_create(data,
236 data->blitter.dsts[i] = bo_create(data,
241 for (i = 0; i < data->n_buffers_load; i++) {
242 intel_copy_bo(data->batch,
243 data->blitter.srcs[i],
244 data->blitter.dsts[i],
249 static void blitter_busy_fini(data_t *data)
253 for (i = 0; i < data->n_buffers_load; i++) {
254 drm_intel_bo_unreference(data->blitter.srcs[i]);
255 drm_intel_bo_unreference(data->blitter.dsts[i]);
258 free(data->blitter.srcs);
259 free(data->blitter.dsts);
260 data->blitter.srcs = NULL;
261 data->blitter.dsts = NULL;
264 static void blitter_copy(data_t *data, drm_intel_bo *src, drm_intel_bo *dst)
266 intel_copy_bo(data->batch, dst, src, WIDTH*HEIGHT*4);
270 void (*busy)(data_t *data);
271 void (*busy_fini)(data_t *data);
272 void (*copy)(data_t *data, drm_intel_bo *src, drm_intel_bo *dst);
276 .busy_fini = render_busy_fini,
280 .busy = blitter_busy,
281 .busy_fini = blitter_busy_fini,
282 .copy = blitter_copy,
286 static void run_test(data_t *data, enum ring r1, enum ring r2, enum test test)
288 struct ring_ops *r1_ops = &ops[r1];
289 struct ring_ops *r2_ops = &ops[r2];
290 drm_intel_bo *a, *b, *c;
292 a = bo_create(data, WIDTH, HEIGHT, 0xa);
293 b = bo_create(data, WIDTH, HEIGHT, 0xb);
294 c = bo_create(data, WIDTH, HEIGHT, 0xc);
297 r1_ops->copy(data, a, b);
300 case TEST_WRITE_READ:
301 r2_ops->copy(data, b, c);
302 bo_check(data, c, 0xa);
304 case TEST_READ_WRITE:
305 r2_ops->copy(data, c, a);
306 bo_check(data, b, 0xa);
308 case TEST_WRITE_WRITE:
309 r2_ops->copy(data, c, b);
310 bo_check(data, b, 0xc);
316 r1_ops->busy_fini(data);
325 } ring_combinations [] = {
331 data.drm_fd = drm_open_any_render();
332 data.devid = intel_get_drm_devid(data.drm_fd);
334 data.n_buffers_load = 1000;
336 data.bufmgr = drm_intel_bufmgr_gem_init(data.drm_fd, 4096);
337 igt_assert(data.bufmgr);
338 drm_intel_bufmgr_gem_enable_reuse(data.bufmgr);
340 data.render.copy = igt_get_render_copyfunc(data.devid);
341 igt_require_f(data.render.copy,
342 "no render-copy function\n");
344 data.batch = intel_batchbuffer_alloc(data.bufmgr, data.devid);
345 igt_assert(data.batch);
348 for (i = 0; i < ARRAY_SIZE(ring_combinations); i++) {
349 struct combination *c = &ring_combinations[i];
351 igt_subtest_f("sync-%s-%s-write-read",
352 ring_name(c->r1), ring_name(c->r2))
353 run_test(&data, c->r1, c->r2, TEST_WRITE_READ);
355 igt_subtest_f("sync-%s-%s-read-write",
356 ring_name(c->r1), ring_name(c->r2))
357 run_test(&data, c->r1, c->r2, TEST_READ_WRITE);
358 igt_subtest_f("sync-%s-%s-write-write",
359 ring_name(c->r1), ring_name(c->r2))
360 run_test(&data, c->r1, c->r2, TEST_WRITE_WRITE);
364 intel_batchbuffer_free(data.batch);
365 drm_intel_bufmgr_destroy(data.bufmgr);