2 * Copyright (c) 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Mika Kuoppala <mika.kuoppala@intel.com>
37 #include <sys/ioctl.h>
43 #include "intel_bufmgr.h"
44 #include "intel_batchbuffer.h"
45 #include "intel_gpu_tools.h"
46 #include "rendercopy.h"
47 #include "igt_debugfs.h"
50 #define RS_BATCH_ACTIVE (1 << 0)
51 #define RS_BATCH_PENDING (1 << 1)
52 #define RS_UNKNOWN (1 << 2)
54 struct local_drm_i915_reset_stats {
63 struct local_drm_i915_gem_context_create {
68 struct local_drm_i915_gem_context_destroy {
75 #define CONTEXT_CREATE_IOCTL DRM_IOWR(DRM_COMMAND_BASE + 0x2d, struct local_drm_i915_gem_context_create)
76 #define CONTEXT_DESTROY_IOCTL DRM_IOWR(DRM_COMMAND_BASE + 0x2e, struct local_drm_i915_gem_context_destroy)
77 #define GET_RESET_STATS_IOCTL DRM_IOWR(DRM_COMMAND_BASE + 0x32, struct local_drm_i915_reset_stats)
79 #define LOCAL_I915_EXEC_VEBOX (4 << 0)
83 static bool gem_has_render(int fd)
88 static bool has_context(const struct target_ring *ring);
90 static const struct target_ring {
92 bool (*present)(int fd);
93 bool (*contexts)(const struct target_ring *ring);
96 { I915_EXEC_RENDER, gem_has_render, has_context, "render" },
97 { I915_EXEC_BLT, gem_has_blt, has_context, "blt" },
98 { I915_EXEC_BSD, gem_has_bsd, has_context, "bsd" },
99 { LOCAL_I915_EXEC_VEBOX, gem_has_vebox, has_context, "vebox" },
102 static bool has_context(const struct target_ring *ring)
104 if(ring->exec == I915_EXEC_RENDER)
110 #define NUM_RINGS (sizeof(rings)/sizeof(struct target_ring))
112 static const struct target_ring *current_ring;
114 static uint32_t context_create(int fd)
116 struct local_drm_i915_gem_context_create create;
119 create.ctx_id = rand();
122 ret = drmIoctl(fd, CONTEXT_CREATE_IOCTL, &create);
123 igt_assert(ret == 0);
125 return create.ctx_id;
128 static int context_destroy(int fd, uint32_t ctx_id)
131 struct local_drm_i915_gem_context_destroy destroy;
133 destroy.ctx_id = ctx_id;
134 destroy.pad = rand();
136 ret = drmIoctl(fd, CONTEXT_DESTROY_IOCTL, &destroy);
143 static int gem_reset_stats(int fd, int ctx_id,
144 struct local_drm_i915_reset_stats *rs)
150 rs->reset_count = rand();
151 rs->batch_active = rand();
152 rs->batch_pending = rand();
156 ret = ioctl(fd, GET_RESET_STATS_IOCTL, rs);
157 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
165 static int gem_reset_status(int fd, int ctx_id)
168 struct local_drm_i915_reset_stats rs;
170 ret = gem_reset_stats(fd, ctx_id, &rs);
175 return RS_BATCH_ACTIVE;
176 if (rs.batch_pending)
177 return RS_BATCH_PENDING;
182 static int gem_exec(int fd, struct drm_i915_gem_execbuffer2 *execbuf)
187 DRM_IOCTL_I915_GEM_EXECBUFFER2,
196 static int exec_valid_ring(int fd, int ctx, int ring)
198 struct drm_i915_gem_execbuffer2 execbuf;
199 struct drm_i915_gem_exec_object2 exec;
202 uint32_t buf[2] = { MI_BATCH_BUFFER_END, 0 };
204 exec.handle = gem_create(fd, 4096);
205 gem_write(fd, exec.handle, 0, buf, sizeof(buf));
206 exec.relocation_count = 0;
214 execbuf.buffers_ptr = (uintptr_t)&exec;
215 execbuf.buffer_count = 1;
216 execbuf.batch_start_offset = 0;
217 execbuf.batch_len = sizeof(buf);
218 execbuf.cliprects_ptr = 0;
219 execbuf.num_cliprects = 0;
222 execbuf.flags = ring;
223 i915_execbuffer2_set_context_id(execbuf, ctx);
226 ret = gem_exec(fd, &execbuf);
233 static int exec_valid(int fd, int ctx)
235 return exec_valid_ring(fd, ctx, current_ring->exec);
238 static void stop_rings(const int mask)
243 igt_assert((mask & ~((1 << NUM_RINGS) - 1)) == 0);
244 igt_assert(snprintf(buf, sizeof(buf), "0x%02x", mask) == 4);
245 fd = igt_debugfs_open("i915_ring_stop", O_WRONLY);
248 igt_assert(write(fd, buf, 4) == 4);
252 #define BUFSIZE (4 * 1024)
253 #define ITEMS (BUFSIZE >> 2)
255 static int ring_to_mask(int ring)
257 for (unsigned i = 0; i < NUM_RINGS; i++) {
258 const struct target_ring *r = &rings[i];
269 static int inject_hang_ring(int fd, int ctx, int ring)
271 struct drm_i915_gem_execbuffer2 execbuf;
272 struct drm_i915_gem_exec_object2 exec;
276 unsigned cmd_len = 2;
280 if (intel_gen(intel_get_drm_devid(fd)) >= 8)
283 buf = malloc(BUFSIZE);
284 igt_assert(buf != NULL);
286 buf[0] = MI_BATCH_BUFFER_END;
289 exec.handle = gem_create(fd, BUFSIZE);
290 gem_write(fd, exec.handle, 0, buf, BUFSIZE);
291 exec.relocation_count = 0;
299 execbuf.buffers_ptr = (uintptr_t)&exec;
300 execbuf.buffer_count = 1;
301 execbuf.batch_start_offset = 0;
302 execbuf.batch_len = BUFSIZE;
303 execbuf.cliprects_ptr = 0;
304 execbuf.num_cliprects = 0;
307 execbuf.flags = ring;
308 i915_execbuffer2_set_context_id(execbuf, ctx);
311 igt_assert(gem_exec(fd, &execbuf) == 0);
313 gtt_off = exec.offset;
315 for (i = 0; i < ITEMS; i++)
318 roff = random() % (ITEMS - cmd_len);
319 buf[roff] = MI_BATCH_BUFFER_START | (cmd_len - 2);
320 buf[roff + 1] = (gtt_off & 0xfffffffc) + (roff << 2);
322 buf[roff + 2] = gtt_off & 0xffffffff00000000ull;
325 printf("loop injected at 0x%lx (off 0x%x, bo_start 0x%lx, bo_end 0x%lx)\n",
326 (long unsigned int)((roff << 2) + gtt_off),
327 roff << 2, (long unsigned int)gtt_off,
328 (long unsigned int)(gtt_off + BUFSIZE - 1));
330 gem_write(fd, exec.handle, 0, buf, BUFSIZE);
332 exec.relocation_count = 0;
340 execbuf.buffers_ptr = (uintptr_t)&exec;
341 execbuf.buffer_count = 1;
342 execbuf.batch_start_offset = 0;
343 execbuf.batch_len = BUFSIZE;
344 execbuf.cliprects_ptr = 0;
345 execbuf.num_cliprects = 0;
348 execbuf.flags = ring;
349 i915_execbuffer2_set_context_id(execbuf, ctx);
352 igt_assert(gem_exec(fd, &execbuf) == 0);
354 igt_assert(gtt_off == exec.offset);
358 stop_rings(ring_to_mask(ring));
363 static int inject_hang(int fd, int ctx)
365 return inject_hang_ring(fd, ctx, current_ring->exec);
368 static int _assert_reset_status(int fd, int ctx, int status)
372 rs = gem_reset_status(fd, ctx);
374 printf("reset status for %d ctx %d returned %d\n",
380 printf("%d:%d reset status %d differs from assumed %d\n",
381 fd, ctx, rs, status);
389 #define assert_reset_status(fd, ctx, status) \
390 igt_assert(_assert_reset_status(fd, ctx, status) == 0)
392 static void test_rs(int num_fds, int hang_index, int rs_assumed_no_hang)
398 igt_assert (num_fds <= MAX_FD);
399 igt_assert (hang_index < MAX_FD);
401 for (i = 0; i < num_fds; i++) {
402 fd[i] = drm_open_any();
406 for (i = 0; i < num_fds; i++)
407 assert_reset_status(fd[i], 0, RS_NO_ERROR);
409 for (i = 0; i < num_fds; i++) {
411 h[i] = inject_hang(fd[i], 0);
413 h[i] = exec_valid(fd[i], 0);
416 gem_sync(fd[num_fds - 1], h[num_fds - 1]);
418 for (i = 0; i < num_fds; i++) {
419 if (hang_index < 0) {
420 assert_reset_status(fd[i], 0, rs_assumed_no_hang);
425 assert_reset_status(fd[i], 0, RS_NO_ERROR);
427 assert_reset_status(fd[i], 0, RS_BATCH_ACTIVE);
429 assert_reset_status(fd[i], 0, RS_BATCH_PENDING);
432 for (i = 0; i < num_fds; i++) {
433 gem_close(fd[i], h[i]);
439 static void test_rs_ctx(int num_fds, int num_ctx, int hang_index,
444 int h[MAX_FD][MAX_CTX];
445 int ctx[MAX_FD][MAX_CTX];
447 igt_assert (num_fds <= MAX_FD);
448 igt_assert (hang_index < MAX_FD);
450 igt_assert (num_ctx <= MAX_CTX);
451 igt_assert (hang_context < MAX_CTX);
453 test_rs(num_fds, -1, RS_NO_ERROR);
455 for (i = 0; i < num_fds; i++) {
456 fd[i] = drm_open_any();
458 assert_reset_status(fd[i], 0, RS_NO_ERROR);
460 for (j = 0; j < num_ctx; j++) {
461 ctx[i][j] = context_create(fd[i]);
465 assert_reset_status(fd[i], 0, RS_NO_ERROR);
468 for (i = 0; i < num_fds; i++) {
470 assert_reset_status(fd[i], 0, RS_NO_ERROR);
472 for (j = 0; j < num_ctx; j++)
473 assert_reset_status(fd[i], ctx[i][j], RS_NO_ERROR);
475 assert_reset_status(fd[i], 0, RS_NO_ERROR);
478 for (i = 0; i < num_fds; i++) {
479 for (j = 0; j < num_ctx; j++) {
480 if (i == hang_index && j == hang_context)
481 h[i][j] = inject_hang(fd[i], ctx[i][j]);
483 h[i][j] = exec_valid(fd[i], ctx[i][j]);
487 gem_sync(fd[num_fds - 1], ctx[num_fds - 1][num_ctx - 1]);
489 for (i = 0; i < num_fds; i++)
490 assert_reset_status(fd[i], 0, RS_NO_ERROR);
492 for (i = 0; i < num_fds; i++) {
493 for (j = 0; j < num_ctx; j++) {
495 assert_reset_status(fd[i], ctx[i][j], RS_NO_ERROR);
496 if (i == hang_index && j < hang_context)
497 assert_reset_status(fd[i], ctx[i][j], RS_NO_ERROR);
498 if (i == hang_index && j == hang_context)
499 assert_reset_status(fd[i], ctx[i][j],
501 if (i == hang_index && j > hang_context)
502 assert_reset_status(fd[i], ctx[i][j],
505 assert_reset_status(fd[i], ctx[i][j],
510 for (i = 0; i < num_fds; i++) {
511 for (j = 0; j < num_ctx; j++) {
512 gem_close(fd[i], h[i][j]);
513 igt_assert(context_destroy(fd[i], ctx[i][j]) == 0);
516 assert_reset_status(fd[i], 0, RS_NO_ERROR);
522 static void test_ban(void)
524 int h1,h2,h3,h4,h5,h6,h7;
527 int active_count = 0, pending_count = 0;
528 struct local_drm_i915_reset_stats rs_bad, rs_good;
530 fd_bad = drm_open_any();
531 igt_assert(fd_bad >= 0);
533 fd_good = drm_open_any();
534 igt_assert(fd_good >= 0);
536 assert_reset_status(fd_bad, 0, RS_NO_ERROR);
537 assert_reset_status(fd_good, 0, RS_NO_ERROR);
539 h1 = exec_valid(fd_bad, 0);
541 h5 = exec_valid(fd_good, 0);
544 assert_reset_status(fd_bad, 0, RS_NO_ERROR);
545 assert_reset_status(fd_good, 0, RS_NO_ERROR);
547 h2 = inject_hang(fd_bad, 0);
550 /* Second hang will be pending for this */
553 h6 = exec_valid(fd_good, 0);
554 h7 = exec_valid(fd_good, 0);
557 h3 = inject_hang(fd_bad, 0);
559 gem_sync(fd_bad, h3);
561 /* This second hand will count as pending */
562 assert_reset_status(fd_bad, 0, RS_BATCH_ACTIVE);
564 h4 = exec_valid(fd_bad, 0);
566 gem_close(fd_bad, h3);
570 /* Should not happen often but sometimes hang is declared too slow
571 * due to our way of faking hang using loop */
574 gem_close(fd_bad, h3);
575 gem_close(fd_bad, h4);
577 printf("retrying for ban (%d)\n", retry);
580 igt_assert(h4 == -EIO);
581 assert_reset_status(fd_bad, 0, RS_BATCH_ACTIVE);
583 gem_sync(fd_good, h7);
584 assert_reset_status(fd_good, 0, RS_BATCH_PENDING);
586 igt_assert(gem_reset_stats(fd_good, 0, &rs_good) == 0);
587 igt_assert(gem_reset_stats(fd_bad, 0, &rs_bad) == 0);
589 igt_assert(rs_bad.batch_active == active_count);
590 igt_assert(rs_bad.batch_pending == pending_count);
591 igt_assert(rs_good.batch_active == 0);
592 igt_assert(rs_good.batch_pending == 2);
594 gem_close(fd_bad, h1);
595 gem_close(fd_bad, h2);
596 gem_close(fd_good, h6);
597 gem_close(fd_good, h7);
599 h1 = exec_valid(fd_good, 0);
601 gem_close(fd_good, h1);
606 igt_assert(gem_reset_status(fd_bad, 0) < 0);
607 igt_assert(gem_reset_status(fd_good, 0) < 0);
610 static void test_ban_ctx(void)
612 int h1,h2,h3,h4,h5,h6,h7;
613 int ctx_good, ctx_bad;
616 int active_count = 0, pending_count = 0;
617 struct local_drm_i915_reset_stats rs_bad, rs_good;
622 assert_reset_status(fd, 0, RS_NO_ERROR);
624 ctx_good = context_create(fd);
625 ctx_bad = context_create(fd);
627 assert_reset_status(fd, 0, RS_NO_ERROR);
628 assert_reset_status(fd, ctx_good, RS_NO_ERROR);
629 assert_reset_status(fd, ctx_bad, RS_NO_ERROR);
631 h1 = exec_valid(fd, ctx_bad);
633 h5 = exec_valid(fd, ctx_good);
636 assert_reset_status(fd, ctx_good, RS_NO_ERROR);
637 assert_reset_status(fd, ctx_bad, RS_NO_ERROR);
639 h2 = inject_hang(fd, ctx_bad);
642 /* Second hang will be pending for this */
645 h6 = exec_valid(fd, ctx_good);
646 h7 = exec_valid(fd, ctx_good);
649 h3 = inject_hang(fd, ctx_bad);
653 /* This second hand will count as pending */
654 assert_reset_status(fd, ctx_bad, RS_BATCH_ACTIVE);
656 h4 = exec_valid(fd, ctx_bad);
662 /* Should not happen often but sometimes hang is declared too slow
663 * due to our way of faking hang using loop */
669 printf("retrying for ban (%d)\n", retry);
672 igt_assert(h4 == -EIO);
673 assert_reset_status(fd, ctx_bad, RS_BATCH_ACTIVE);
676 assert_reset_status(fd, ctx_good, RS_BATCH_PENDING);
678 igt_assert(gem_reset_stats(fd, ctx_good, &rs_good) == 0);
679 igt_assert(gem_reset_stats(fd, ctx_bad, &rs_bad) == 0);
681 igt_assert(rs_bad.batch_active == active_count);
682 igt_assert(rs_bad.batch_pending == pending_count);
683 igt_assert(rs_good.batch_active == 0);
684 igt_assert(rs_good.batch_pending == 2);
691 h1 = exec_valid(fd, ctx_good);
695 igt_assert(context_destroy(fd, ctx_good) == 0);
696 igt_assert(context_destroy(fd, ctx_bad) == 0);
697 igt_assert(gem_reset_status(fd, ctx_good) < 0);
698 igt_assert(gem_reset_status(fd, ctx_bad) < 0);
699 igt_assert(exec_valid(fd, ctx_good) < 0);
700 igt_assert(exec_valid(fd, ctx_bad) < 0);
705 static void test_unrelated_ctx(void)
709 int ctx_guilty, ctx_unrelated;
711 fd1 = drm_open_any();
712 fd2 = drm_open_any();
713 assert_reset_status(fd1, 0, RS_NO_ERROR);
714 assert_reset_status(fd2, 0, RS_NO_ERROR);
715 ctx_guilty = context_create(fd1);
716 ctx_unrelated = context_create(fd2);
718 assert_reset_status(fd1, ctx_guilty, RS_NO_ERROR);
719 assert_reset_status(fd2, ctx_unrelated, RS_NO_ERROR);
721 h1 = inject_hang(fd1, ctx_guilty);
724 assert_reset_status(fd1, ctx_guilty, RS_BATCH_ACTIVE);
725 assert_reset_status(fd2, ctx_unrelated, RS_NO_ERROR);
727 h2 = exec_valid(fd2, ctx_unrelated);
730 assert_reset_status(fd1, ctx_guilty, RS_BATCH_ACTIVE);
731 assert_reset_status(fd2, ctx_unrelated, RS_NO_ERROR);
735 igt_assert(context_destroy(fd1, ctx_guilty) == 0);
736 igt_assert(context_destroy(fd2, ctx_unrelated) == 0);
742 static int get_reset_count(int fd, int ctx)
745 struct local_drm_i915_reset_stats rs;
747 ret = gem_reset_stats(fd, ctx, &rs);
751 return rs.reset_count;
754 static void test_close_pending_ctx(void)
761 ctx = context_create(fd);
763 assert_reset_status(fd, ctx, RS_NO_ERROR);
765 h = inject_hang(fd, ctx);
767 igt_assert(context_destroy(fd, ctx) == 0);
768 igt_assert(context_destroy(fd, ctx) == -ENOENT);
774 static void test_close_pending(void)
781 assert_reset_status(fd, 0, RS_NO_ERROR);
783 h = inject_hang(fd, 0);
790 static void exec_noop_on_each_ring(int fd, const bool reverse)
792 uint32_t batch[2] = {MI_BATCH_BUFFER_END, 0};
794 struct drm_i915_gem_execbuffer2 execbuf;
795 struct drm_i915_gem_exec_object2 exec[1];
797 handle = gem_create(fd, 4096);
798 gem_write(fd, handle, 0, batch, sizeof(batch));
800 exec[0].handle = handle;
801 exec[0].relocation_count = 0;
802 exec[0].relocs_ptr = 0;
803 exec[0].alignment = 0;
809 execbuf.buffers_ptr = (uintptr_t)exec;
810 execbuf.buffer_count = 1;
811 execbuf.batch_start_offset = 0;
812 execbuf.batch_len = 8;
813 execbuf.cliprects_ptr = 0;
814 execbuf.num_cliprects = 0;
818 i915_execbuffer2_set_context_id(execbuf, 0);
821 for (unsigned i = 0; i < NUM_RINGS; i++) {
822 const struct target_ring *ring;
824 ring = reverse ? &rings[NUM_RINGS - 1 - i] : &rings[i];
826 if (ring->present(fd)) {
827 execbuf.flags = ring->exec;
828 do_ioctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf);
832 gem_sync(fd, handle);
833 gem_close(fd, handle);
836 static void test_close_pending_fork(const bool reverse)
844 assert_reset_status(fd, 0, RS_NO_ERROR);
846 h = inject_hang(fd, 0);
851 /* Avoid helpers as we need to kill the child
852 * without any extra signal handling on behalf of
857 const int fd2 = drm_open_any();
858 igt_assert(fd2 >= 0);
860 /* The crucial component is that we schedule the same noop batch
861 * on each ring. This exercises batch_obj reference counting,
862 * when gpu is reset and ring lists are cleared.
864 exec_noop_on_each_ring(fd2, reverse);
872 /* Kill the child to reduce refcounts on
880 /* Then we just wait on hang to happen */
884 h = exec_valid(fd, 0);
892 static void test_reset_count(const bool create_ctx)
900 ctx = context_create(fd);
904 assert_reset_status(fd, ctx, RS_NO_ERROR);
906 c1 = get_reset_count(fd, ctx);
909 h = inject_hang(fd, ctx);
913 assert_reset_status(fd, ctx, RS_BATCH_ACTIVE);
914 c2 = get_reset_count(fd, ctx);
916 igt_assert(c2 == (c1 + 1));
921 c2 = get_reset_count(fd, ctx);
924 igt_assert(c2 == -EPERM);
934 context_destroy(fd, ctx);
939 static int _test_params(int fd, int ctx, uint32_t flags, uint32_t pad)
941 struct local_drm_i915_reset_stats rs;
946 rs.reset_count = rand();
947 rs.batch_active = rand();
948 rs.batch_pending = rand();
952 ret = ioctl(fd, GET_RESET_STATS_IOCTL, &rs);
953 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
961 typedef enum { root = 0, user } cap_t;
963 static void test_param_ctx(const int fd, const int ctx, const cap_t cap)
965 const uint32_t bad = rand() + 1;
969 igt_assert(_test_params(fd, ctx, 0, 0) == 0);
971 igt_assert(_test_params(fd, ctx, 0, 0) == -EPERM);
974 igt_assert(_test_params(fd, ctx, 0, bad) == -EINVAL);
975 igt_assert(_test_params(fd, ctx, bad, 0) == -EINVAL);
976 igt_assert(_test_params(fd, ctx, bad, bad) == -EINVAL);
979 static void check_params(const int fd, const int ctx, cap_t cap)
981 igt_assert(ioctl(fd, GET_RESET_STATS_IOCTL, 0) == -1);
982 igt_assert(_test_params(fd, 0xbadbad, 0, 0) == -ENOENT);
984 test_param_ctx(fd, 0, cap);
985 test_param_ctx(fd, ctx, cap);
988 static void _test_param(const int fd, const int ctx)
990 check_params(fd, ctx, root);
993 check_params(fd, ctx, root);
997 check_params(fd, ctx, user);
1000 check_params(fd, ctx, root);
1005 static void test_params(void)
1009 fd = drm_open_any();
1010 igt_assert(fd >= 0);
1011 ctx = context_create(fd);
1013 _test_param(fd, ctx);
1018 #define RING_HAS_CONTEXTS current_ring->contexts(current_ring)
1019 #define RUN_CTX_TEST(...) do { igt_skip_on(RING_HAS_CONTEXTS == false); __VA_ARGS__; } while (0)
1025 struct local_drm_i915_gem_context_create create;
1029 igt_skip_on_simulation();
1032 fd = drm_open_any();
1033 devid = intel_get_drm_devid(fd);
1034 igt_require_f(intel_gen(devid) >= 4,
1035 "Architecture %d too old\n", intel_gen(devid));
1037 ret = drmIoctl(fd, CONTEXT_CREATE_IOCTL, &create);
1038 igt_skip_on_f(ret != 0 && (errno == ENODEV || errno == EINVAL),
1039 "Kernel is too old, or contexts not supported: %s\n",
1043 igt_subtest("params")
1046 for (int i = 0; i < NUM_RINGS; i++) {
1049 current_ring = &rings[i];
1050 name = current_ring->name;
1053 gem_require_ring(fd, current_ring->exec);
1055 igt_subtest_f("reset-stats-%s", name)
1058 igt_subtest_f("reset-stats-ctx-%s", name)
1059 RUN_CTX_TEST(test_rs_ctx(4, 4, 1, 2));
1061 igt_subtest_f("ban-%s", name)
1064 igt_subtest_f("ban-ctx-%s", name)
1065 RUN_CTX_TEST(test_ban_ctx());
1067 igt_subtest_f("reset-count-%s", name)
1068 test_reset_count(false);
1070 igt_subtest_f("reset-count-ctx-%s", name)
1071 RUN_CTX_TEST(test_reset_count(true));
1073 igt_subtest_f("unrelated-ctx-%s", name)
1074 RUN_CTX_TEST(test_unrelated_ctx());
1076 igt_subtest_f("close-pending-%s", name) {
1077 test_close_pending();
1078 gem_quiescent_gpu(fd);
1081 igt_subtest_f("close-pending-ctx-%s", name) {
1082 RUN_CTX_TEST(test_close_pending_ctx());
1083 gem_quiescent_gpu(fd);
1086 igt_subtest_f("close-pending-fork-%s", name) {
1087 test_close_pending_fork(true);
1088 test_close_pending_fork(false);