2 * Copyright (c) 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Mika Kuoppala <mika.kuoppala@intel.com>
37 #include <sys/ioctl.h>
43 #include "intel_bufmgr.h"
44 #include "intel_batchbuffer.h"
45 #include "intel_gpu_tools.h"
46 #include "rendercopy.h"
47 #include "igt_debugfs.h"
50 #define RS_BATCH_ACTIVE (1 << 0)
51 #define RS_BATCH_PENDING (1 << 1)
52 #define RS_UNKNOWN (1 << 2)
54 struct local_drm_i915_reset_stats {
63 struct local_drm_i915_gem_context_create {
68 struct local_drm_i915_gem_context_destroy {
75 #define CONTEXT_CREATE_IOCTL DRM_IOWR(DRM_COMMAND_BASE + 0x2d, struct local_drm_i915_gem_context_create)
76 #define CONTEXT_DESTROY_IOCTL DRM_IOWR(DRM_COMMAND_BASE + 0x2e, struct local_drm_i915_gem_context_destroy)
77 #define GET_RESET_STATS_IOCTL DRM_IOWR(DRM_COMMAND_BASE + 0x32, struct local_drm_i915_reset_stats)
79 static igt_debugfs_t dfs;
81 #define LOCAL_I915_EXEC_VEBOX (4 << 0)
85 static bool gem_has_render(int fd)
90 static bool has_context(const struct target_ring *ring);
92 static const struct target_ring {
94 bool (*present)(int fd);
95 bool (*contexts)(const struct target_ring *ring);
98 { I915_EXEC_RENDER, gem_has_render, has_context, "render" },
99 { I915_EXEC_BLT, gem_has_blt, has_context, "blt" },
100 { I915_EXEC_BSD, gem_has_bsd, has_context, "bsd" },
101 { LOCAL_I915_EXEC_VEBOX, gem_has_vebox, has_context, "vebox" },
104 static bool has_context(const struct target_ring *ring)
106 if(ring->exec == I915_EXEC_RENDER)
112 #define NUM_RINGS (sizeof(rings)/sizeof(struct target_ring))
114 static const struct target_ring *current_ring;
116 static uint32_t context_create(int fd)
118 struct local_drm_i915_gem_context_create create;
121 create.ctx_id = rand();
124 ret = drmIoctl(fd, CONTEXT_CREATE_IOCTL, &create);
125 igt_assert(ret == 0);
127 return create.ctx_id;
130 static int context_destroy(int fd, uint32_t ctx_id)
133 struct local_drm_i915_gem_context_destroy destroy;
135 destroy.ctx_id = ctx_id;
136 destroy.pad = rand();
138 ret = drmIoctl(fd, CONTEXT_DESTROY_IOCTL, &destroy);
145 static int gem_reset_stats(int fd, int ctx_id,
146 struct local_drm_i915_reset_stats *rs)
152 rs->reset_count = rand();
153 rs->batch_active = rand();
154 rs->batch_pending = rand();
158 ret = ioctl(fd, GET_RESET_STATS_IOCTL, rs);
159 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
167 static int gem_reset_status(int fd, int ctx_id)
170 struct local_drm_i915_reset_stats rs;
172 ret = gem_reset_stats(fd, ctx_id, &rs);
177 return RS_BATCH_ACTIVE;
178 if (rs.batch_pending)
179 return RS_BATCH_PENDING;
184 static int gem_exec(int fd, struct drm_i915_gem_execbuffer2 *execbuf)
189 DRM_IOCTL_I915_GEM_EXECBUFFER2,
198 static int exec_valid_ring(int fd, int ctx, int ring)
200 struct drm_i915_gem_execbuffer2 execbuf;
201 struct drm_i915_gem_exec_object2 exec;
204 uint32_t buf[2] = { MI_BATCH_BUFFER_END, 0 };
206 exec.handle = gem_create(fd, 4096);
207 gem_write(fd, exec.handle, 0, buf, sizeof(buf));
208 exec.relocation_count = 0;
216 execbuf.buffers_ptr = (uintptr_t)&exec;
217 execbuf.buffer_count = 1;
218 execbuf.batch_start_offset = 0;
219 execbuf.batch_len = sizeof(buf);
220 execbuf.cliprects_ptr = 0;
221 execbuf.num_cliprects = 0;
224 execbuf.flags = ring;
225 i915_execbuffer2_set_context_id(execbuf, ctx);
228 ret = gem_exec(fd, &execbuf);
235 static int exec_valid(int fd, int ctx)
237 return exec_valid_ring(fd, ctx, current_ring->exec);
240 static void stop_rings(void)
244 fd = igt_debugfs_open(&dfs, "i915_ring_stop", O_WRONLY);
247 igt_assert(write(fd, "0xff", 4) == 4);
251 #define BUFSIZE (4 * 1024)
252 #define ITEMS (BUFSIZE >> 2)
254 static int inject_hang_ring(int fd, int ctx, int ring)
256 struct drm_i915_gem_execbuffer2 execbuf;
257 struct drm_i915_gem_exec_object2 exec;
261 unsigned cmd_len = 2;
265 if (intel_gen(intel_get_drm_devid(fd)) >= 8)
268 buf = malloc(BUFSIZE);
269 igt_assert(buf != NULL);
271 buf[0] = MI_BATCH_BUFFER_END;
274 exec.handle = gem_create(fd, BUFSIZE);
275 gem_write(fd, exec.handle, 0, buf, BUFSIZE);
276 exec.relocation_count = 0;
284 execbuf.buffers_ptr = (uintptr_t)&exec;
285 execbuf.buffer_count = 1;
286 execbuf.batch_start_offset = 0;
287 execbuf.batch_len = BUFSIZE;
288 execbuf.cliprects_ptr = 0;
289 execbuf.num_cliprects = 0;
292 execbuf.flags = ring;
293 i915_execbuffer2_set_context_id(execbuf, ctx);
296 igt_assert(gem_exec(fd, &execbuf) == 0);
298 gtt_off = exec.offset;
300 for (i = 0; i < ITEMS; i++)
303 roff = random() % (ITEMS - cmd_len);
304 buf[roff] = MI_BATCH_BUFFER_START | (cmd_len - 2);
305 buf[roff + 1] = (gtt_off & 0xfffffffc) + (roff << 2);
307 buf[roff + 2] = gtt_off & 0xffffffff00000000ull;
310 printf("loop injected at 0x%lx (off 0x%x, bo_start 0x%lx, bo_end 0x%lx)\n",
311 (long unsigned int)((roff << 2) + gtt_off),
312 roff << 2, (long unsigned int)gtt_off,
313 (long unsigned int)(gtt_off + BUFSIZE - 1));
315 gem_write(fd, exec.handle, 0, buf, BUFSIZE);
317 exec.relocation_count = 0;
325 execbuf.buffers_ptr = (uintptr_t)&exec;
326 execbuf.buffer_count = 1;
327 execbuf.batch_start_offset = 0;
328 execbuf.batch_len = BUFSIZE;
329 execbuf.cliprects_ptr = 0;
330 execbuf.num_cliprects = 0;
333 execbuf.flags = ring;
334 i915_execbuffer2_set_context_id(execbuf, ctx);
337 igt_assert(gem_exec(fd, &execbuf) == 0);
339 igt_assert(gtt_off == exec.offset);
348 static int inject_hang(int fd, int ctx)
350 return inject_hang_ring(fd, ctx, current_ring->exec);
353 static int _assert_reset_status(int fd, int ctx, int status)
357 rs = gem_reset_status(fd, ctx);
359 printf("reset status for %d ctx %d returned %d\n",
365 printf("%d:%d reset status %d differs from assumed %d\n",
366 fd, ctx, rs, status);
374 #define assert_reset_status(fd, ctx, status) \
375 igt_assert(_assert_reset_status(fd, ctx, status) == 0)
377 static void test_rs(int num_fds, int hang_index, int rs_assumed_no_hang)
383 igt_assert (num_fds <= MAX_FD);
384 igt_assert (hang_index < MAX_FD);
386 for (i = 0; i < num_fds; i++) {
387 fd[i] = drm_open_any();
391 for (i = 0; i < num_fds; i++)
392 assert_reset_status(fd[i], 0, RS_NO_ERROR);
394 for (i = 0; i < num_fds; i++) {
396 h[i] = inject_hang(fd[i], 0);
398 h[i] = exec_valid(fd[i], 0);
401 gem_sync(fd[num_fds - 1], h[num_fds - 1]);
403 for (i = 0; i < num_fds; i++) {
404 if (hang_index < 0) {
405 assert_reset_status(fd[i], 0, rs_assumed_no_hang);
410 assert_reset_status(fd[i], 0, RS_NO_ERROR);
412 assert_reset_status(fd[i], 0, RS_BATCH_ACTIVE);
414 assert_reset_status(fd[i], 0, RS_BATCH_PENDING);
417 for (i = 0; i < num_fds; i++) {
418 gem_close(fd[i], h[i]);
424 static void test_rs_ctx(int num_fds, int num_ctx, int hang_index,
429 int h[MAX_FD][MAX_CTX];
430 int ctx[MAX_FD][MAX_CTX];
432 igt_assert (num_fds <= MAX_FD);
433 igt_assert (hang_index < MAX_FD);
435 igt_assert (num_ctx <= MAX_CTX);
436 igt_assert (hang_context < MAX_CTX);
438 test_rs(num_fds, -1, RS_NO_ERROR);
440 for (i = 0; i < num_fds; i++) {
441 fd[i] = drm_open_any();
443 assert_reset_status(fd[i], 0, RS_NO_ERROR);
445 for (j = 0; j < num_ctx; j++) {
446 ctx[i][j] = context_create(fd[i]);
450 assert_reset_status(fd[i], 0, RS_NO_ERROR);
453 for (i = 0; i < num_fds; i++) {
455 assert_reset_status(fd[i], 0, RS_NO_ERROR);
457 for (j = 0; j < num_ctx; j++)
458 assert_reset_status(fd[i], ctx[i][j], RS_NO_ERROR);
460 assert_reset_status(fd[i], 0, RS_NO_ERROR);
463 for (i = 0; i < num_fds; i++) {
464 for (j = 0; j < num_ctx; j++) {
465 if (i == hang_index && j == hang_context)
466 h[i][j] = inject_hang(fd[i], ctx[i][j]);
468 h[i][j] = exec_valid(fd[i], ctx[i][j]);
472 gem_sync(fd[num_fds - 1], ctx[num_fds - 1][num_ctx - 1]);
474 for (i = 0; i < num_fds; i++)
475 assert_reset_status(fd[i], 0, RS_NO_ERROR);
477 for (i = 0; i < num_fds; i++) {
478 for (j = 0; j < num_ctx; j++) {
480 assert_reset_status(fd[i], ctx[i][j], RS_NO_ERROR);
481 if (i == hang_index && j < hang_context)
482 assert_reset_status(fd[i], ctx[i][j], RS_NO_ERROR);
483 if (i == hang_index && j == hang_context)
484 assert_reset_status(fd[i], ctx[i][j],
486 if (i == hang_index && j > hang_context)
487 assert_reset_status(fd[i], ctx[i][j],
490 assert_reset_status(fd[i], ctx[i][j],
495 for (i = 0; i < num_fds; i++) {
496 for (j = 0; j < num_ctx; j++) {
497 gem_close(fd[i], h[i][j]);
498 igt_assert(context_destroy(fd[i], ctx[i][j]) == 0);
501 assert_reset_status(fd[i], 0, RS_NO_ERROR);
507 static void test_ban(void)
509 int h1,h2,h3,h4,h5,h6,h7;
512 int active_count = 0, pending_count = 0;
513 struct local_drm_i915_reset_stats rs_bad, rs_good;
515 fd_bad = drm_open_any();
516 igt_assert(fd_bad >= 0);
518 fd_good = drm_open_any();
519 igt_assert(fd_good >= 0);
521 assert_reset_status(fd_bad, 0, RS_NO_ERROR);
522 assert_reset_status(fd_good, 0, RS_NO_ERROR);
524 h1 = exec_valid(fd_bad, 0);
526 h5 = exec_valid(fd_good, 0);
529 assert_reset_status(fd_bad, 0, RS_NO_ERROR);
530 assert_reset_status(fd_good, 0, RS_NO_ERROR);
532 h2 = inject_hang(fd_bad, 0);
535 /* Second hang will be pending for this */
538 h6 = exec_valid(fd_good, 0);
539 h7 = exec_valid(fd_good, 0);
542 h3 = inject_hang(fd_bad, 0);
544 gem_sync(fd_bad, h3);
546 /* This second hand will count as pending */
547 assert_reset_status(fd_bad, 0, RS_BATCH_ACTIVE);
549 h4 = exec_valid(fd_bad, 0);
551 gem_close(fd_bad, h3);
555 /* Should not happen often but sometimes hang is declared too slow
556 * due to our way of faking hang using loop */
559 gem_close(fd_bad, h3);
560 gem_close(fd_bad, h4);
562 printf("retrying for ban (%d)\n", retry);
565 igt_assert(h4 == -EIO);
566 assert_reset_status(fd_bad, 0, RS_BATCH_ACTIVE);
568 gem_sync(fd_good, h7);
569 assert_reset_status(fd_good, 0, RS_BATCH_PENDING);
571 igt_assert(gem_reset_stats(fd_good, 0, &rs_good) == 0);
572 igt_assert(gem_reset_stats(fd_bad, 0, &rs_bad) == 0);
574 igt_assert(rs_bad.batch_active == active_count);
575 igt_assert(rs_bad.batch_pending == pending_count);
576 igt_assert(rs_good.batch_active == 0);
577 igt_assert(rs_good.batch_pending == 2);
579 gem_close(fd_bad, h1);
580 gem_close(fd_bad, h2);
581 gem_close(fd_good, h6);
582 gem_close(fd_good, h7);
584 h1 = exec_valid(fd_good, 0);
586 gem_close(fd_good, h1);
591 igt_assert(gem_reset_status(fd_bad, 0) < 0);
592 igt_assert(gem_reset_status(fd_good, 0) < 0);
595 static void test_ban_ctx(void)
597 int h1,h2,h3,h4,h5,h6,h7;
598 int ctx_good, ctx_bad;
601 int active_count = 0, pending_count = 0;
602 struct local_drm_i915_reset_stats rs_bad, rs_good;
607 assert_reset_status(fd, 0, RS_NO_ERROR);
609 ctx_good = context_create(fd);
610 ctx_bad = context_create(fd);
612 assert_reset_status(fd, 0, RS_NO_ERROR);
613 assert_reset_status(fd, ctx_good, RS_NO_ERROR);
614 assert_reset_status(fd, ctx_bad, RS_NO_ERROR);
616 h1 = exec_valid(fd, ctx_bad);
618 h5 = exec_valid(fd, ctx_good);
621 assert_reset_status(fd, ctx_good, RS_NO_ERROR);
622 assert_reset_status(fd, ctx_bad, RS_NO_ERROR);
624 h2 = inject_hang(fd, ctx_bad);
627 /* Second hang will be pending for this */
630 h6 = exec_valid(fd, ctx_good);
631 h7 = exec_valid(fd, ctx_good);
634 h3 = inject_hang(fd, ctx_bad);
638 /* This second hand will count as pending */
639 assert_reset_status(fd, ctx_bad, RS_BATCH_ACTIVE);
641 h4 = exec_valid(fd, ctx_bad);
647 /* Should not happen often but sometimes hang is declared too slow
648 * due to our way of faking hang using loop */
654 printf("retrying for ban (%d)\n", retry);
657 igt_assert(h4 == -EIO);
658 assert_reset_status(fd, ctx_bad, RS_BATCH_ACTIVE);
661 assert_reset_status(fd, ctx_good, RS_BATCH_PENDING);
663 igt_assert(gem_reset_stats(fd, ctx_good, &rs_good) == 0);
664 igt_assert(gem_reset_stats(fd, ctx_bad, &rs_bad) == 0);
666 igt_assert(rs_bad.batch_active == active_count);
667 igt_assert(rs_bad.batch_pending == pending_count);
668 igt_assert(rs_good.batch_active == 0);
669 igt_assert(rs_good.batch_pending == 2);
676 h1 = exec_valid(fd, ctx_good);
680 igt_assert(context_destroy(fd, ctx_good) == 0);
681 igt_assert(context_destroy(fd, ctx_bad) == 0);
682 igt_assert(gem_reset_status(fd, ctx_good) < 0);
683 igt_assert(gem_reset_status(fd, ctx_bad) < 0);
684 igt_assert(exec_valid(fd, ctx_good) < 0);
685 igt_assert(exec_valid(fd, ctx_bad) < 0);
690 static void test_unrelated_ctx(void)
694 int ctx_guilty, ctx_unrelated;
696 fd1 = drm_open_any();
697 fd2 = drm_open_any();
698 assert_reset_status(fd1, 0, RS_NO_ERROR);
699 assert_reset_status(fd2, 0, RS_NO_ERROR);
700 ctx_guilty = context_create(fd1);
701 ctx_unrelated = context_create(fd2);
703 assert_reset_status(fd1, ctx_guilty, RS_NO_ERROR);
704 assert_reset_status(fd2, ctx_unrelated, RS_NO_ERROR);
706 h1 = inject_hang(fd1, ctx_guilty);
709 assert_reset_status(fd1, ctx_guilty, RS_BATCH_ACTIVE);
710 assert_reset_status(fd2, ctx_unrelated, RS_NO_ERROR);
712 h2 = exec_valid(fd2, ctx_unrelated);
715 assert_reset_status(fd1, ctx_guilty, RS_BATCH_ACTIVE);
716 assert_reset_status(fd2, ctx_unrelated, RS_NO_ERROR);
720 igt_assert(context_destroy(fd1, ctx_guilty) == 0);
721 igt_assert(context_destroy(fd2, ctx_unrelated) == 0);
727 static int get_reset_count(int fd, int ctx)
730 struct local_drm_i915_reset_stats rs;
732 ret = gem_reset_stats(fd, ctx, &rs);
736 return rs.reset_count;
739 static void test_close_pending_ctx(void)
746 ctx = context_create(fd);
748 assert_reset_status(fd, ctx, RS_NO_ERROR);
750 h = inject_hang(fd, ctx);
752 igt_assert(context_destroy(fd, ctx) == 0);
753 igt_assert(context_destroy(fd, ctx) == -ENOENT);
759 static void test_close_pending(void)
766 assert_reset_status(fd, 0, RS_NO_ERROR);
768 h = inject_hang(fd, 0);
775 static void exec_noop_on_each_ring(int fd, const bool reverse)
777 uint32_t batch[2] = {MI_BATCH_BUFFER_END, 0};
779 struct drm_i915_gem_execbuffer2 execbuf;
780 struct drm_i915_gem_exec_object2 exec[1];
782 handle = gem_create(fd, 4096);
783 gem_write(fd, handle, 0, batch, sizeof(batch));
785 exec[0].handle = handle;
786 exec[0].relocation_count = 0;
787 exec[0].relocs_ptr = 0;
788 exec[0].alignment = 0;
794 execbuf.buffers_ptr = (uintptr_t)exec;
795 execbuf.buffer_count = 1;
796 execbuf.batch_start_offset = 0;
797 execbuf.batch_len = 8;
798 execbuf.cliprects_ptr = 0;
799 execbuf.num_cliprects = 0;
803 i915_execbuffer2_set_context_id(execbuf, 0);
806 for (unsigned i = 0; i < NUM_RINGS; i++) {
807 const struct target_ring *ring;
809 ring = reverse ? &rings[NUM_RINGS - 1 - i] : &rings[i];
811 if (ring->present(fd)) {
812 execbuf.flags = ring->exec;
813 do_ioctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf);
817 gem_sync(fd, handle);
818 gem_close(fd, handle);
821 static void test_close_pending_fork(const bool reverse)
829 assert_reset_status(fd, 0, RS_NO_ERROR);
831 h = inject_hang(fd, 0);
836 /* Avoid helpers as we need to kill the child
837 * without any extra signal handling on behalf of
842 const int fd2 = drm_open_any();
843 igt_assert(fd2 >= 0);
845 /* The crucial component is that we schedule the same noop batch
846 * on each ring. This exercises batch_obj reference counting,
847 * when gpu is reset and ring lists are cleared.
849 exec_noop_on_each_ring(fd2, reverse);
857 /* Kill the child to reduce refcounts on
865 /* Then we just wait on hang to happen */
869 h = exec_valid(fd, 0);
877 static void test_reset_count(const bool create_ctx)
885 ctx = context_create(fd);
889 assert_reset_status(fd, ctx, RS_NO_ERROR);
891 c1 = get_reset_count(fd, ctx);
894 h = inject_hang(fd, ctx);
898 assert_reset_status(fd, ctx, RS_BATCH_ACTIVE);
899 c2 = get_reset_count(fd, ctx);
901 igt_assert(c2 == (c1 + 1));
906 c2 = get_reset_count(fd, ctx);
909 igt_assert(c2 == -EPERM);
919 context_destroy(fd, ctx);
924 static int _test_params(int fd, int ctx, uint32_t flags, uint32_t pad)
926 struct local_drm_i915_reset_stats rs;
931 rs.reset_count = rand();
932 rs.batch_active = rand();
933 rs.batch_pending = rand();
937 ret = ioctl(fd, GET_RESET_STATS_IOCTL, &rs);
938 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
946 typedef enum { root = 0, user } cap_t;
948 static void test_param_ctx(const int fd, const int ctx, const cap_t cap)
950 const uint32_t bad = rand() + 1;
954 igt_assert(_test_params(fd, ctx, 0, 0) == 0);
956 igt_assert(_test_params(fd, ctx, 0, 0) == -EPERM);
959 igt_assert(_test_params(fd, ctx, 0, bad) == -EINVAL);
960 igt_assert(_test_params(fd, ctx, bad, 0) == -EINVAL);
961 igt_assert(_test_params(fd, ctx, bad, bad) == -EINVAL);
964 static void check_params(const int fd, const int ctx, cap_t cap)
966 igt_assert(ioctl(fd, GET_RESET_STATS_IOCTL, 0) == -1);
967 igt_assert(_test_params(fd, 0xbadbad, 0, 0) == -ENOENT);
969 test_param_ctx(fd, 0, cap);
970 test_param_ctx(fd, ctx, cap);
973 static void _test_param(const int fd, const int ctx)
975 check_params(fd, ctx, root);
978 check_params(fd, ctx, root);
982 check_params(fd, ctx, user);
985 check_params(fd, ctx, root);
990 static void test_params(void)
996 ctx = context_create(fd);
998 _test_param(fd, ctx);
1003 #define RING_HAS_CONTEXTS current_ring->contexts(current_ring)
1004 #define RUN_CTX_TEST(...) do { igt_skip_on(RING_HAS_CONTEXTS == false); __VA_ARGS__; } while (0)
1008 struct local_drm_i915_gem_context_create create;
1012 igt_skip_on_simulation();
1016 fd = drm_open_any();
1017 devid = intel_get_drm_devid(fd);
1018 igt_require_f(intel_gen(devid) >= 4,
1019 "Architecture %d too old\n", intel_gen(devid));
1021 ret = drmIoctl(fd, CONTEXT_CREATE_IOCTL, &create);
1022 igt_skip_on_f(ret != 0 && (errno == ENODEV || errno == EINVAL),
1023 "Kernel is too old, or contexts not supported: %s\n",
1026 assert(igt_debugfs_init(&dfs) == 0);
1031 igt_subtest("params")
1034 for (int i = 0; i < NUM_RINGS; i++) {
1038 current_ring = &rings[i];
1039 name = current_ring->name;
1041 fd = drm_open_any();
1042 gem_require_ring(fd, current_ring->exec);
1044 igt_subtest_f("reset-stats-%s", name)
1047 igt_subtest_f("reset-stats-ctx-%s", name)
1048 RUN_CTX_TEST(test_rs_ctx(4, 4, 1, 2));
1050 igt_subtest_f("ban-%s", name)
1053 igt_subtest_f("ban-ctx-%s", name)
1054 RUN_CTX_TEST(test_ban_ctx());
1056 igt_subtest_f("reset-count-%s", name)
1057 test_reset_count(false);
1059 igt_subtest_f("reset-count-ctx-%s", name)
1060 RUN_CTX_TEST(test_reset_count(true));
1062 igt_subtest_f("unrelated-ctx-%s", name)
1063 RUN_CTX_TEST(test_unrelated_ctx());
1065 igt_subtest_f("close-pending-%s", name) {
1066 test_close_pending();
1067 gem_quiescent_gpu(fd);
1070 igt_subtest_f("close-pending-ctx-%s", name) {
1071 RUN_CTX_TEST(test_close_pending_ctx());
1072 gem_quiescent_gpu(fd);
1075 igt_subtest_f("close-pending-fork-%s", name) {
1076 test_close_pending_fork(true);
1077 test_close_pending_fork(false);