2 * Copyright (c) 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Mika Kuoppala <mika.kuoppala@intel.com>
38 #include <sys/ioctl.h>
45 #include "igt_debugfs.h"
46 #include "intel_bufmgr.h"
47 #include "intel_batchbuffer.h"
48 #include "intel_gpu_tools.h"
51 #define RS_BATCH_ACTIVE (1 << 0)
52 #define RS_BATCH_PENDING (1 << 1)
53 #define RS_UNKNOWN (1 << 2)
55 struct local_drm_i915_reset_stats {
64 struct local_drm_i915_gem_context_create {
69 struct local_drm_i915_gem_context_destroy {
76 #define CONTEXT_CREATE_IOCTL DRM_IOWR(DRM_COMMAND_BASE + 0x2d, struct local_drm_i915_gem_context_create)
77 #define CONTEXT_DESTROY_IOCTL DRM_IOWR(DRM_COMMAND_BASE + 0x2e, struct local_drm_i915_gem_context_destroy)
78 #define GET_RESET_STATS_IOCTL DRM_IOWR(DRM_COMMAND_BASE + 0x32, struct local_drm_i915_reset_stats)
80 #define LOCAL_I915_EXEC_VEBOX (4 << 0)
84 static bool gem_has_render(int fd)
89 static bool has_context(const struct target_ring *ring);
91 static const struct target_ring {
93 bool (*present)(int fd);
94 bool (*contexts)(const struct target_ring *ring);
97 { I915_EXEC_RENDER, gem_has_render, has_context, "render" },
98 { I915_EXEC_BLT, gem_has_blt, has_context, "blt" },
99 { I915_EXEC_BSD, gem_has_bsd, has_context, "bsd" },
100 { LOCAL_I915_EXEC_VEBOX, gem_has_vebox, has_context, "vebox" },
103 static bool has_context(const struct target_ring *ring)
105 if(ring->exec == I915_EXEC_RENDER)
111 #define NUM_RINGS (sizeof(rings)/sizeof(struct target_ring))
113 static const struct target_ring *current_ring;
115 static uint32_t context_create(int fd)
117 struct local_drm_i915_gem_context_create create;
120 create.ctx_id = rand();
123 ret = drmIoctl(fd, CONTEXT_CREATE_IOCTL, &create);
124 igt_assert(ret == 0);
126 return create.ctx_id;
129 static int context_destroy(int fd, uint32_t ctx_id)
132 struct local_drm_i915_gem_context_destroy destroy;
134 destroy.ctx_id = ctx_id;
135 destroy.pad = rand();
137 ret = drmIoctl(fd, CONTEXT_DESTROY_IOCTL, &destroy);
144 static int gem_reset_stats(int fd, int ctx_id,
145 struct local_drm_i915_reset_stats *rs)
151 rs->reset_count = rand();
152 rs->batch_active = rand();
153 rs->batch_pending = rand();
157 ret = ioctl(fd, GET_RESET_STATS_IOCTL, rs);
158 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
166 static int gem_reset_status(int fd, int ctx_id)
169 struct local_drm_i915_reset_stats rs;
171 ret = gem_reset_stats(fd, ctx_id, &rs);
176 return RS_BATCH_ACTIVE;
177 if (rs.batch_pending)
178 return RS_BATCH_PENDING;
183 static int gem_exec(int fd, struct drm_i915_gem_execbuffer2 *execbuf)
188 DRM_IOCTL_I915_GEM_EXECBUFFER2,
197 static int exec_valid_ring(int fd, int ctx, int ring)
199 struct drm_i915_gem_execbuffer2 execbuf;
200 struct drm_i915_gem_exec_object2 exec;
203 uint32_t buf[2] = { MI_BATCH_BUFFER_END, 0 };
205 exec.handle = gem_create(fd, 4096);
206 gem_write(fd, exec.handle, 0, buf, sizeof(buf));
207 exec.relocation_count = 0;
215 execbuf.buffers_ptr = (uintptr_t)&exec;
216 execbuf.buffer_count = 1;
217 execbuf.batch_start_offset = 0;
218 execbuf.batch_len = sizeof(buf);
219 execbuf.cliprects_ptr = 0;
220 execbuf.num_cliprects = 0;
223 execbuf.flags = ring;
224 i915_execbuffer2_set_context_id(execbuf, ctx);
227 ret = gem_exec(fd, &execbuf);
234 static int exec_valid(int fd, int ctx)
236 return exec_valid_ring(fd, ctx, current_ring->exec);
239 static void stop_rings(const int mask)
244 igt_assert((mask & ~((1 << NUM_RINGS) - 1)) == 0);
245 igt_assert(snprintf(buf, sizeof(buf), "0x%02x", mask) == 4);
246 fd = igt_debugfs_open("i915_ring_stop", O_WRONLY);
249 igt_assert(write(fd, buf, 4) == 4);
253 #define BUFSIZE (4 * 1024)
254 #define ITEMS (BUFSIZE >> 2)
256 static int ring_to_mask(int ring)
258 for (unsigned i = 0; i < NUM_RINGS; i++) {
259 const struct target_ring *r = &rings[i];
270 static int inject_hang_ring(int fd, int ctx, int ring)
272 struct drm_i915_gem_execbuffer2 execbuf;
273 struct drm_i915_gem_exec_object2 exec;
277 unsigned cmd_len = 2;
281 if (intel_gen(intel_get_drm_devid(fd)) >= 8)
284 buf = malloc(BUFSIZE);
285 igt_assert(buf != NULL);
287 buf[0] = MI_BATCH_BUFFER_END;
290 exec.handle = gem_create(fd, BUFSIZE);
291 gem_write(fd, exec.handle, 0, buf, BUFSIZE);
292 exec.relocation_count = 0;
300 execbuf.buffers_ptr = (uintptr_t)&exec;
301 execbuf.buffer_count = 1;
302 execbuf.batch_start_offset = 0;
303 execbuf.batch_len = BUFSIZE;
304 execbuf.cliprects_ptr = 0;
305 execbuf.num_cliprects = 0;
308 execbuf.flags = ring;
309 i915_execbuffer2_set_context_id(execbuf, ctx);
312 igt_assert(gem_exec(fd, &execbuf) == 0);
314 gtt_off = exec.offset;
316 for (i = 0; i < ITEMS; i++)
319 roff = random() % (ITEMS - cmd_len);
320 buf[roff] = MI_BATCH_BUFFER_START | (cmd_len - 2);
321 buf[roff + 1] = (gtt_off & 0xfffffffc) + (roff << 2);
323 buf[roff + 2] = gtt_off & 0xffffffff00000000ull;
326 printf("loop injected at 0x%lx (off 0x%x, bo_start 0x%lx, bo_end 0x%lx)\n",
327 (long unsigned int)((roff << 2) + gtt_off),
328 roff << 2, (long unsigned int)gtt_off,
329 (long unsigned int)(gtt_off + BUFSIZE - 1));
331 gem_write(fd, exec.handle, 0, buf, BUFSIZE);
333 exec.relocation_count = 0;
341 execbuf.buffers_ptr = (uintptr_t)&exec;
342 execbuf.buffer_count = 1;
343 execbuf.batch_start_offset = 0;
344 execbuf.batch_len = BUFSIZE;
345 execbuf.cliprects_ptr = 0;
346 execbuf.num_cliprects = 0;
349 execbuf.flags = ring;
350 i915_execbuffer2_set_context_id(execbuf, ctx);
353 igt_assert(gem_exec(fd, &execbuf) == 0);
355 igt_assert(gtt_off == exec.offset);
359 stop_rings(ring_to_mask(ring));
364 static int inject_hang(int fd, int ctx)
366 return inject_hang_ring(fd, ctx, current_ring->exec);
369 static int _assert_reset_status(int fd, int ctx, int status)
373 rs = gem_reset_status(fd, ctx);
375 printf("reset status for %d ctx %d returned %d\n",
381 printf("%d:%d reset status %d differs from assumed %d\n",
382 fd, ctx, rs, status);
390 #define assert_reset_status(fd, ctx, status) \
391 igt_assert(_assert_reset_status(fd, ctx, status) == 0)
393 static void test_rs(int num_fds, int hang_index, int rs_assumed_no_hang)
399 igt_assert (num_fds <= MAX_FD);
400 igt_assert (hang_index < MAX_FD);
402 for (i = 0; i < num_fds; i++) {
403 fd[i] = drm_open_any();
407 for (i = 0; i < num_fds; i++)
408 assert_reset_status(fd[i], 0, RS_NO_ERROR);
410 for (i = 0; i < num_fds; i++) {
412 h[i] = inject_hang(fd[i], 0);
414 h[i] = exec_valid(fd[i], 0);
417 gem_sync(fd[num_fds - 1], h[num_fds - 1]);
419 for (i = 0; i < num_fds; i++) {
420 if (hang_index < 0) {
421 assert_reset_status(fd[i], 0, rs_assumed_no_hang);
426 assert_reset_status(fd[i], 0, RS_NO_ERROR);
428 assert_reset_status(fd[i], 0, RS_BATCH_ACTIVE);
430 assert_reset_status(fd[i], 0, RS_BATCH_PENDING);
433 for (i = 0; i < num_fds; i++) {
434 gem_close(fd[i], h[i]);
440 static void test_rs_ctx(int num_fds, int num_ctx, int hang_index,
445 int h[MAX_FD][MAX_CTX];
446 int ctx[MAX_FD][MAX_CTX];
448 igt_assert (num_fds <= MAX_FD);
449 igt_assert (hang_index < MAX_FD);
451 igt_assert (num_ctx <= MAX_CTX);
452 igt_assert (hang_context < MAX_CTX);
454 test_rs(num_fds, -1, RS_NO_ERROR);
456 for (i = 0; i < num_fds; i++) {
457 fd[i] = drm_open_any();
459 assert_reset_status(fd[i], 0, RS_NO_ERROR);
461 for (j = 0; j < num_ctx; j++) {
462 ctx[i][j] = context_create(fd[i]);
466 assert_reset_status(fd[i], 0, RS_NO_ERROR);
469 for (i = 0; i < num_fds; i++) {
471 assert_reset_status(fd[i], 0, RS_NO_ERROR);
473 for (j = 0; j < num_ctx; j++)
474 assert_reset_status(fd[i], ctx[i][j], RS_NO_ERROR);
476 assert_reset_status(fd[i], 0, RS_NO_ERROR);
479 for (i = 0; i < num_fds; i++) {
480 for (j = 0; j < num_ctx; j++) {
481 if (i == hang_index && j == hang_context)
482 h[i][j] = inject_hang(fd[i], ctx[i][j]);
484 h[i][j] = exec_valid(fd[i], ctx[i][j]);
488 gem_sync(fd[num_fds - 1], ctx[num_fds - 1][num_ctx - 1]);
490 for (i = 0; i < num_fds; i++)
491 assert_reset_status(fd[i], 0, RS_NO_ERROR);
493 for (i = 0; i < num_fds; i++) {
494 for (j = 0; j < num_ctx; j++) {
496 assert_reset_status(fd[i], ctx[i][j], RS_NO_ERROR);
497 if (i == hang_index && j < hang_context)
498 assert_reset_status(fd[i], ctx[i][j], RS_NO_ERROR);
499 if (i == hang_index && j == hang_context)
500 assert_reset_status(fd[i], ctx[i][j],
502 if (i == hang_index && j > hang_context)
503 assert_reset_status(fd[i], ctx[i][j],
506 assert_reset_status(fd[i], ctx[i][j],
511 for (i = 0; i < num_fds; i++) {
512 for (j = 0; j < num_ctx; j++) {
513 gem_close(fd[i], h[i][j]);
514 igt_assert(context_destroy(fd[i], ctx[i][j]) == 0);
517 assert_reset_status(fd[i], 0, RS_NO_ERROR);
523 static void test_ban(void)
525 int h1,h2,h3,h4,h5,h6,h7;
528 int active_count = 0, pending_count = 0;
529 struct local_drm_i915_reset_stats rs_bad, rs_good;
531 fd_bad = drm_open_any();
532 igt_assert(fd_bad >= 0);
534 fd_good = drm_open_any();
535 igt_assert(fd_good >= 0);
537 assert_reset_status(fd_bad, 0, RS_NO_ERROR);
538 assert_reset_status(fd_good, 0, RS_NO_ERROR);
540 h1 = exec_valid(fd_bad, 0);
542 h5 = exec_valid(fd_good, 0);
545 assert_reset_status(fd_bad, 0, RS_NO_ERROR);
546 assert_reset_status(fd_good, 0, RS_NO_ERROR);
548 h2 = inject_hang(fd_bad, 0);
551 /* Second hang will be pending for this */
554 h6 = exec_valid(fd_good, 0);
555 h7 = exec_valid(fd_good, 0);
558 h3 = inject_hang(fd_bad, 0);
560 gem_sync(fd_bad, h3);
562 /* This second hand will count as pending */
563 assert_reset_status(fd_bad, 0, RS_BATCH_ACTIVE);
565 h4 = exec_valid(fd_bad, 0);
567 gem_close(fd_bad, h3);
571 /* Should not happen often but sometimes hang is declared too slow
572 * due to our way of faking hang using loop */
575 gem_close(fd_bad, h3);
576 gem_close(fd_bad, h4);
578 printf("retrying for ban (%d)\n", retry);
581 igt_assert(h4 == -EIO);
582 assert_reset_status(fd_bad, 0, RS_BATCH_ACTIVE);
584 gem_sync(fd_good, h7);
585 assert_reset_status(fd_good, 0, RS_BATCH_PENDING);
587 igt_assert(gem_reset_stats(fd_good, 0, &rs_good) == 0);
588 igt_assert(gem_reset_stats(fd_bad, 0, &rs_bad) == 0);
590 igt_assert(rs_bad.batch_active == active_count);
591 igt_assert(rs_bad.batch_pending == pending_count);
592 igt_assert(rs_good.batch_active == 0);
593 igt_assert(rs_good.batch_pending == 2);
595 gem_close(fd_bad, h1);
596 gem_close(fd_bad, h2);
597 gem_close(fd_good, h6);
598 gem_close(fd_good, h7);
600 h1 = exec_valid(fd_good, 0);
602 gem_close(fd_good, h1);
607 igt_assert(gem_reset_status(fd_bad, 0) < 0);
608 igt_assert(gem_reset_status(fd_good, 0) < 0);
611 static void test_ban_ctx(void)
613 int h1,h2,h3,h4,h5,h6,h7;
614 int ctx_good, ctx_bad;
617 int active_count = 0, pending_count = 0;
618 struct local_drm_i915_reset_stats rs_bad, rs_good;
623 assert_reset_status(fd, 0, RS_NO_ERROR);
625 ctx_good = context_create(fd);
626 ctx_bad = context_create(fd);
628 assert_reset_status(fd, 0, RS_NO_ERROR);
629 assert_reset_status(fd, ctx_good, RS_NO_ERROR);
630 assert_reset_status(fd, ctx_bad, RS_NO_ERROR);
632 h1 = exec_valid(fd, ctx_bad);
634 h5 = exec_valid(fd, ctx_good);
637 assert_reset_status(fd, ctx_good, RS_NO_ERROR);
638 assert_reset_status(fd, ctx_bad, RS_NO_ERROR);
640 h2 = inject_hang(fd, ctx_bad);
643 /* Second hang will be pending for this */
646 h6 = exec_valid(fd, ctx_good);
647 h7 = exec_valid(fd, ctx_good);
650 h3 = inject_hang(fd, ctx_bad);
654 /* This second hand will count as pending */
655 assert_reset_status(fd, ctx_bad, RS_BATCH_ACTIVE);
657 h4 = exec_valid(fd, ctx_bad);
663 /* Should not happen often but sometimes hang is declared too slow
664 * due to our way of faking hang using loop */
670 printf("retrying for ban (%d)\n", retry);
673 igt_assert(h4 == -EIO);
674 assert_reset_status(fd, ctx_bad, RS_BATCH_ACTIVE);
677 assert_reset_status(fd, ctx_good, RS_BATCH_PENDING);
679 igt_assert(gem_reset_stats(fd, ctx_good, &rs_good) == 0);
680 igt_assert(gem_reset_stats(fd, ctx_bad, &rs_bad) == 0);
682 igt_assert(rs_bad.batch_active == active_count);
683 igt_assert(rs_bad.batch_pending == pending_count);
684 igt_assert(rs_good.batch_active == 0);
685 igt_assert(rs_good.batch_pending == 2);
692 h1 = exec_valid(fd, ctx_good);
696 igt_assert(context_destroy(fd, ctx_good) == 0);
697 igt_assert(context_destroy(fd, ctx_bad) == 0);
698 igt_assert(gem_reset_status(fd, ctx_good) < 0);
699 igt_assert(gem_reset_status(fd, ctx_bad) < 0);
700 igt_assert(exec_valid(fd, ctx_good) < 0);
701 igt_assert(exec_valid(fd, ctx_bad) < 0);
706 static void test_unrelated_ctx(void)
710 int ctx_guilty, ctx_unrelated;
712 fd1 = drm_open_any();
713 fd2 = drm_open_any();
714 assert_reset_status(fd1, 0, RS_NO_ERROR);
715 assert_reset_status(fd2, 0, RS_NO_ERROR);
716 ctx_guilty = context_create(fd1);
717 ctx_unrelated = context_create(fd2);
719 assert_reset_status(fd1, ctx_guilty, RS_NO_ERROR);
720 assert_reset_status(fd2, ctx_unrelated, RS_NO_ERROR);
722 h1 = inject_hang(fd1, ctx_guilty);
725 assert_reset_status(fd1, ctx_guilty, RS_BATCH_ACTIVE);
726 assert_reset_status(fd2, ctx_unrelated, RS_NO_ERROR);
728 h2 = exec_valid(fd2, ctx_unrelated);
731 assert_reset_status(fd1, ctx_guilty, RS_BATCH_ACTIVE);
732 assert_reset_status(fd2, ctx_unrelated, RS_NO_ERROR);
736 igt_assert(context_destroy(fd1, ctx_guilty) == 0);
737 igt_assert(context_destroy(fd2, ctx_unrelated) == 0);
743 static int get_reset_count(int fd, int ctx)
746 struct local_drm_i915_reset_stats rs;
748 ret = gem_reset_stats(fd, ctx, &rs);
752 return rs.reset_count;
755 static void test_close_pending_ctx(void)
762 ctx = context_create(fd);
764 assert_reset_status(fd, ctx, RS_NO_ERROR);
766 h = inject_hang(fd, ctx);
768 igt_assert(context_destroy(fd, ctx) == 0);
769 igt_assert(context_destroy(fd, ctx) == -ENOENT);
775 static void test_close_pending(void)
782 assert_reset_status(fd, 0, RS_NO_ERROR);
784 h = inject_hang(fd, 0);
791 static void exec_noop_on_each_ring(int fd, const bool reverse)
793 uint32_t batch[2] = {MI_BATCH_BUFFER_END, 0};
795 struct drm_i915_gem_execbuffer2 execbuf;
796 struct drm_i915_gem_exec_object2 exec[1];
798 handle = gem_create(fd, 4096);
799 gem_write(fd, handle, 0, batch, sizeof(batch));
801 exec[0].handle = handle;
802 exec[0].relocation_count = 0;
803 exec[0].relocs_ptr = 0;
804 exec[0].alignment = 0;
810 execbuf.buffers_ptr = (uintptr_t)exec;
811 execbuf.buffer_count = 1;
812 execbuf.batch_start_offset = 0;
813 execbuf.batch_len = 8;
814 execbuf.cliprects_ptr = 0;
815 execbuf.num_cliprects = 0;
819 i915_execbuffer2_set_context_id(execbuf, 0);
822 for (unsigned i = 0; i < NUM_RINGS; i++) {
823 const struct target_ring *ring;
825 ring = reverse ? &rings[NUM_RINGS - 1 - i] : &rings[i];
827 if (ring->present(fd)) {
828 execbuf.flags = ring->exec;
829 do_ioctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf);
833 gem_sync(fd, handle);
834 gem_close(fd, handle);
837 static void test_close_pending_fork(const bool reverse)
845 assert_reset_status(fd, 0, RS_NO_ERROR);
847 h = inject_hang(fd, 0);
852 /* Avoid helpers as we need to kill the child
853 * without any extra signal handling on behalf of
858 const int fd2 = drm_open_any();
859 igt_assert(fd2 >= 0);
861 /* The crucial component is that we schedule the same noop batch
862 * on each ring. This exercises batch_obj reference counting,
863 * when gpu is reset and ring lists are cleared.
865 exec_noop_on_each_ring(fd2, reverse);
873 /* Kill the child to reduce refcounts on
881 /* Then we just wait on hang to happen */
885 h = exec_valid(fd, 0);
893 static void test_reset_count(const bool create_ctx)
901 ctx = context_create(fd);
905 assert_reset_status(fd, ctx, RS_NO_ERROR);
907 c1 = get_reset_count(fd, ctx);
910 h = inject_hang(fd, ctx);
914 assert_reset_status(fd, ctx, RS_BATCH_ACTIVE);
915 c2 = get_reset_count(fd, ctx);
917 igt_assert(c2 == (c1 + 1));
922 c2 = get_reset_count(fd, ctx);
925 igt_assert(c2 == -EPERM);
935 context_destroy(fd, ctx);
940 static int _test_params(int fd, int ctx, uint32_t flags, uint32_t pad)
942 struct local_drm_i915_reset_stats rs;
947 rs.reset_count = rand();
948 rs.batch_active = rand();
949 rs.batch_pending = rand();
953 ret = ioctl(fd, GET_RESET_STATS_IOCTL, &rs);
954 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
962 typedef enum { root = 0, user } cap_t;
964 static void test_param_ctx(const int fd, const int ctx, const cap_t cap)
966 const uint32_t bad = rand() + 1;
970 igt_assert(_test_params(fd, ctx, 0, 0) == 0);
972 igt_assert(_test_params(fd, ctx, 0, 0) == -EPERM);
975 igt_assert(_test_params(fd, ctx, 0, bad) == -EINVAL);
976 igt_assert(_test_params(fd, ctx, bad, 0) == -EINVAL);
977 igt_assert(_test_params(fd, ctx, bad, bad) == -EINVAL);
980 static void check_params(const int fd, const int ctx, cap_t cap)
982 igt_assert(ioctl(fd, GET_RESET_STATS_IOCTL, 0) == -1);
983 igt_assert(_test_params(fd, 0xbadbad, 0, 0) == -ENOENT);
985 test_param_ctx(fd, 0, cap);
986 test_param_ctx(fd, ctx, cap);
989 static void _test_param(const int fd, const int ctx)
991 check_params(fd, ctx, root);
994 check_params(fd, ctx, root);
998 check_params(fd, ctx, user);
1001 check_params(fd, ctx, root);
1006 static void test_params(void)
1010 fd = drm_open_any();
1011 igt_assert(fd >= 0);
1012 ctx = context_create(fd);
1014 _test_param(fd, ctx);
1019 #define RING_HAS_CONTEXTS current_ring->contexts(current_ring)
1020 #define RUN_CTX_TEST(...) do { igt_skip_on(RING_HAS_CONTEXTS == false); __VA_ARGS__; } while (0)
1026 struct local_drm_i915_gem_context_create create;
1030 igt_skip_on_simulation();
1033 fd = drm_open_any();
1034 devid = intel_get_drm_devid(fd);
1035 igt_require_f(intel_gen(devid) >= 4,
1036 "Architecture %d too old\n", intel_gen(devid));
1038 ret = drmIoctl(fd, CONTEXT_CREATE_IOCTL, &create);
1039 igt_skip_on_f(ret != 0 && (errno == ENODEV || errno == EINVAL),
1040 "Kernel is too old, or contexts not supported: %s\n",
1044 igt_subtest("params")
1047 for (int i = 0; i < NUM_RINGS; i++) {
1050 current_ring = &rings[i];
1051 name = current_ring->name;
1054 gem_require_ring(fd, current_ring->exec);
1056 igt_subtest_f("reset-stats-%s", name)
1059 igt_subtest_f("reset-stats-ctx-%s", name)
1060 RUN_CTX_TEST(test_rs_ctx(4, 4, 1, 2));
1062 igt_subtest_f("ban-%s", name)
1065 igt_subtest_f("ban-ctx-%s", name)
1066 RUN_CTX_TEST(test_ban_ctx());
1068 igt_subtest_f("reset-count-%s", name)
1069 test_reset_count(false);
1071 igt_subtest_f("reset-count-ctx-%s", name)
1072 RUN_CTX_TEST(test_reset_count(true));
1074 igt_subtest_f("unrelated-ctx-%s", name)
1075 RUN_CTX_TEST(test_unrelated_ctx());
1077 igt_subtest_f("close-pending-%s", name) {
1078 test_close_pending();
1079 gem_quiescent_gpu(fd);
1082 igt_subtest_f("close-pending-ctx-%s", name) {
1083 RUN_CTX_TEST(test_close_pending_ctx());
1084 gem_quiescent_gpu(fd);
1087 igt_subtest_f("close-pending-fork-%s", name) {
1088 test_close_pending_fork(true);
1089 test_close_pending_fork(false);