2 * Copyright (c) 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Mika Kuoppala <mika.kuoppala@intel.com>
38 #include <sys/ioctl.h>
43 #include "ioctl_wrappers.h"
45 #include "igt_debugfs.h"
46 #include "intel_chipset.h"
51 #define RS_BATCH_ACTIVE (1 << 0)
52 #define RS_BATCH_PENDING (1 << 1)
53 #define RS_UNKNOWN (1 << 2)
55 static uint32_t devid;
56 static bool hw_contexts;
58 struct local_drm_i915_reset_stats {
67 struct local_drm_i915_gem_context_create {
72 struct local_drm_i915_gem_context_destroy {
79 #define CONTEXT_CREATE_IOCTL DRM_IOWR(DRM_COMMAND_BASE + 0x2d, struct local_drm_i915_gem_context_create)
80 #define CONTEXT_DESTROY_IOCTL DRM_IOWR(DRM_COMMAND_BASE + 0x2e, struct local_drm_i915_gem_context_destroy)
81 #define GET_RESET_STATS_IOCTL DRM_IOWR(DRM_COMMAND_BASE + 0x32, struct local_drm_i915_reset_stats)
83 #define LOCAL_I915_EXEC_VEBOX (4 << 0)
87 static bool gem_has_render(int fd)
92 static bool has_context(const struct target_ring *ring);
94 static const struct target_ring {
96 bool (*present)(int fd);
97 bool (*contexts)(const struct target_ring *ring);
100 { I915_EXEC_RENDER, gem_has_render, has_context, "render" },
101 { I915_EXEC_BLT, gem_has_blt, has_context, "blt" },
102 { I915_EXEC_BSD, gem_has_bsd, has_context, "bsd" },
103 { LOCAL_I915_EXEC_VEBOX, gem_has_vebox, has_context, "vebox" },
106 static bool has_context(const struct target_ring *ring)
111 if(ring->exec == I915_EXEC_RENDER)
117 #define NUM_RINGS (sizeof(rings)/sizeof(struct target_ring))
119 static const struct target_ring *current_ring;
121 static uint32_t context_create(int fd)
123 struct local_drm_i915_gem_context_create create;
126 create.ctx_id = rand();
129 ret = drmIoctl(fd, CONTEXT_CREATE_IOCTL, &create);
130 igt_assert(ret == 0);
132 return create.ctx_id;
135 static int context_destroy(int fd, uint32_t ctx_id)
138 struct local_drm_i915_gem_context_destroy destroy;
140 destroy.ctx_id = ctx_id;
141 destroy.pad = rand();
143 ret = drmIoctl(fd, CONTEXT_DESTROY_IOCTL, &destroy);
150 static int gem_reset_stats(int fd, int ctx_id,
151 struct local_drm_i915_reset_stats *rs)
157 rs->reset_count = rand();
158 rs->batch_active = rand();
159 rs->batch_pending = rand();
163 ret = ioctl(fd, GET_RESET_STATS_IOCTL, rs);
164 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
172 static int gem_reset_status(int fd, int ctx_id)
175 struct local_drm_i915_reset_stats rs;
177 ret = gem_reset_stats(fd, ctx_id, &rs);
182 return RS_BATCH_ACTIVE;
183 if (rs.batch_pending)
184 return RS_BATCH_PENDING;
189 static int gem_exec(int fd, struct drm_i915_gem_execbuffer2 *execbuf)
194 DRM_IOCTL_I915_GEM_EXECBUFFER2,
203 static int exec_valid_ring(int fd, int ctx, int ring)
205 struct drm_i915_gem_execbuffer2 execbuf;
206 struct drm_i915_gem_exec_object2 exec;
209 uint32_t buf[2] = { MI_BATCH_BUFFER_END, 0 };
211 exec.handle = gem_create(fd, 4096);
212 gem_write(fd, exec.handle, 0, buf, sizeof(buf));
213 exec.relocation_count = 0;
221 execbuf.buffers_ptr = (uintptr_t)&exec;
222 execbuf.buffer_count = 1;
223 execbuf.batch_start_offset = 0;
224 execbuf.batch_len = sizeof(buf);
225 execbuf.cliprects_ptr = 0;
226 execbuf.num_cliprects = 0;
229 execbuf.flags = ring;
230 i915_execbuffer2_set_context_id(execbuf, ctx);
233 ret = gem_exec(fd, &execbuf);
240 static int exec_valid(int fd, int ctx)
242 return exec_valid_ring(fd, ctx, current_ring->exec);
245 static void stop_rings(const int mask)
250 igt_assert((mask & ~((1 << NUM_RINGS) - 1)) == 0);
251 igt_assert(snprintf(buf, sizeof(buf), "0x%02x", mask) == 4);
252 fd = igt_debugfs_open("i915_ring_stop", O_WRONLY);
255 igt_assert(write(fd, buf, 4) == 4);
259 #define BUFSIZE (4 * 1024)
260 #define ITEMS (BUFSIZE >> 2)
262 static int ring_to_mask(int ring)
264 for (unsigned i = 0; i < NUM_RINGS; i++) {
265 const struct target_ring *r = &rings[i];
276 static int inject_hang_ring(int fd, int ctx, int ring)
278 struct drm_i915_gem_execbuffer2 execbuf;
279 struct drm_i915_gem_exec_object2 exec;
283 unsigned cmd_len = 2;
287 if (intel_gen(devid) >= 8)
290 buf = malloc(BUFSIZE);
291 igt_assert(buf != NULL);
293 buf[0] = MI_BATCH_BUFFER_END;
296 exec.handle = gem_create(fd, BUFSIZE);
297 gem_write(fd, exec.handle, 0, buf, BUFSIZE);
298 exec.relocation_count = 0;
306 execbuf.buffers_ptr = (uintptr_t)&exec;
307 execbuf.buffer_count = 1;
308 execbuf.batch_start_offset = 0;
309 execbuf.batch_len = BUFSIZE;
310 execbuf.cliprects_ptr = 0;
311 execbuf.num_cliprects = 0;
314 execbuf.flags = ring;
315 i915_execbuffer2_set_context_id(execbuf, ctx);
318 igt_assert(gem_exec(fd, &execbuf) == 0);
320 gtt_off = exec.offset;
322 for (i = 0; i < ITEMS; i++)
325 roff = random() % (ITEMS - cmd_len);
326 buf[roff] = MI_BATCH_BUFFER_START | (cmd_len - 2);
327 buf[roff + 1] = (gtt_off & 0xfffffffc) + (roff << 2);
329 buf[roff + 2] = gtt_off & 0xffffffff00000000ull;
332 printf("loop injected at 0x%lx (off 0x%x, bo_start 0x%lx, bo_end 0x%lx)\n",
333 (long unsigned int)((roff << 2) + gtt_off),
334 roff << 2, (long unsigned int)gtt_off,
335 (long unsigned int)(gtt_off + BUFSIZE - 1));
337 gem_write(fd, exec.handle, 0, buf, BUFSIZE);
339 exec.relocation_count = 0;
347 execbuf.buffers_ptr = (uintptr_t)&exec;
348 execbuf.buffer_count = 1;
349 execbuf.batch_start_offset = 0;
350 execbuf.batch_len = BUFSIZE;
351 execbuf.cliprects_ptr = 0;
352 execbuf.num_cliprects = 0;
355 execbuf.flags = ring;
356 i915_execbuffer2_set_context_id(execbuf, ctx);
359 igt_assert(gem_exec(fd, &execbuf) == 0);
361 igt_assert(gtt_off == exec.offset);
365 stop_rings(ring_to_mask(ring));
370 static int inject_hang(int fd, int ctx)
372 return inject_hang_ring(fd, ctx, current_ring->exec);
375 static int _assert_reset_status(int fd, int ctx, int status)
379 rs = gem_reset_status(fd, ctx);
381 printf("reset status for %d ctx %d returned %d\n",
387 printf("%d:%d reset status %d differs from assumed %d\n",
388 fd, ctx, rs, status);
396 #define assert_reset_status(fd, ctx, status) \
397 igt_assert(_assert_reset_status(fd, ctx, status) == 0)
399 static void test_rs(int num_fds, int hang_index, int rs_assumed_no_hang)
405 igt_assert (num_fds <= MAX_FD);
406 igt_assert (hang_index < MAX_FD);
408 for (i = 0; i < num_fds; i++) {
409 fd[i] = drm_open_any();
413 for (i = 0; i < num_fds; i++)
414 assert_reset_status(fd[i], 0, RS_NO_ERROR);
416 for (i = 0; i < num_fds; i++) {
418 h[i] = inject_hang(fd[i], 0);
420 h[i] = exec_valid(fd[i], 0);
423 gem_sync(fd[num_fds - 1], h[num_fds - 1]);
425 for (i = 0; i < num_fds; i++) {
426 if (hang_index < 0) {
427 assert_reset_status(fd[i], 0, rs_assumed_no_hang);
432 assert_reset_status(fd[i], 0, RS_NO_ERROR);
434 assert_reset_status(fd[i], 0, RS_BATCH_ACTIVE);
436 assert_reset_status(fd[i], 0, RS_BATCH_PENDING);
439 for (i = 0; i < num_fds; i++) {
440 gem_close(fd[i], h[i]);
446 static void test_rs_ctx(int num_fds, int num_ctx, int hang_index,
451 int h[MAX_FD][MAX_CTX];
452 int ctx[MAX_FD][MAX_CTX];
454 igt_assert (num_fds <= MAX_FD);
455 igt_assert (hang_index < MAX_FD);
457 igt_assert (num_ctx <= MAX_CTX);
458 igt_assert (hang_context < MAX_CTX);
460 test_rs(num_fds, -1, RS_NO_ERROR);
462 for (i = 0; i < num_fds; i++) {
463 fd[i] = drm_open_any();
465 assert_reset_status(fd[i], 0, RS_NO_ERROR);
467 for (j = 0; j < num_ctx; j++) {
468 ctx[i][j] = context_create(fd[i]);
472 assert_reset_status(fd[i], 0, RS_NO_ERROR);
475 for (i = 0; i < num_fds; i++) {
477 assert_reset_status(fd[i], 0, RS_NO_ERROR);
479 for (j = 0; j < num_ctx; j++)
480 assert_reset_status(fd[i], ctx[i][j], RS_NO_ERROR);
482 assert_reset_status(fd[i], 0, RS_NO_ERROR);
485 for (i = 0; i < num_fds; i++) {
486 for (j = 0; j < num_ctx; j++) {
487 if (i == hang_index && j == hang_context)
488 h[i][j] = inject_hang(fd[i], ctx[i][j]);
490 h[i][j] = exec_valid(fd[i], ctx[i][j]);
494 gem_sync(fd[num_fds - 1], ctx[num_fds - 1][num_ctx - 1]);
496 for (i = 0; i < num_fds; i++)
497 assert_reset_status(fd[i], 0, RS_NO_ERROR);
499 for (i = 0; i < num_fds; i++) {
500 for (j = 0; j < num_ctx; j++) {
502 assert_reset_status(fd[i], ctx[i][j], RS_NO_ERROR);
503 if (i == hang_index && j < hang_context)
504 assert_reset_status(fd[i], ctx[i][j], RS_NO_ERROR);
505 if (i == hang_index && j == hang_context)
506 assert_reset_status(fd[i], ctx[i][j],
508 if (i == hang_index && j > hang_context)
509 assert_reset_status(fd[i], ctx[i][j],
512 assert_reset_status(fd[i], ctx[i][j],
517 for (i = 0; i < num_fds; i++) {
518 for (j = 0; j < num_ctx; j++) {
519 gem_close(fd[i], h[i][j]);
520 igt_assert(context_destroy(fd[i], ctx[i][j]) == 0);
523 assert_reset_status(fd[i], 0, RS_NO_ERROR);
529 static void test_ban(void)
531 int h1,h2,h3,h4,h5,h6,h7;
534 int active_count = 0, pending_count = 0;
535 struct local_drm_i915_reset_stats rs_bad, rs_good;
537 fd_bad = drm_open_any();
538 igt_assert(fd_bad >= 0);
540 fd_good = drm_open_any();
541 igt_assert(fd_good >= 0);
543 assert_reset_status(fd_bad, 0, RS_NO_ERROR);
544 assert_reset_status(fd_good, 0, RS_NO_ERROR);
546 h1 = exec_valid(fd_bad, 0);
548 h5 = exec_valid(fd_good, 0);
551 assert_reset_status(fd_bad, 0, RS_NO_ERROR);
552 assert_reset_status(fd_good, 0, RS_NO_ERROR);
554 h2 = inject_hang(fd_bad, 0);
557 /* Second hang will be pending for this */
560 h6 = exec_valid(fd_good, 0);
561 h7 = exec_valid(fd_good, 0);
564 h3 = inject_hang(fd_bad, 0);
566 gem_sync(fd_bad, h3);
568 /* This second hand will count as pending */
569 assert_reset_status(fd_bad, 0, RS_BATCH_ACTIVE);
571 h4 = exec_valid(fd_bad, 0);
573 gem_close(fd_bad, h3);
577 /* Should not happen often but sometimes hang is declared too slow
578 * due to our way of faking hang using loop */
581 gem_close(fd_bad, h3);
582 gem_close(fd_bad, h4);
584 printf("retrying for ban (%d)\n", retry);
587 igt_assert(h4 == -EIO);
588 assert_reset_status(fd_bad, 0, RS_BATCH_ACTIVE);
590 gem_sync(fd_good, h7);
591 assert_reset_status(fd_good, 0, RS_BATCH_PENDING);
593 igt_assert(gem_reset_stats(fd_good, 0, &rs_good) == 0);
594 igt_assert(gem_reset_stats(fd_bad, 0, &rs_bad) == 0);
596 igt_assert(rs_bad.batch_active == active_count);
597 igt_assert(rs_bad.batch_pending == pending_count);
598 igt_assert(rs_good.batch_active == 0);
599 igt_assert(rs_good.batch_pending == 2);
601 gem_close(fd_bad, h1);
602 gem_close(fd_bad, h2);
603 gem_close(fd_good, h6);
604 gem_close(fd_good, h7);
606 h1 = exec_valid(fd_good, 0);
608 gem_close(fd_good, h1);
613 igt_assert(gem_reset_status(fd_bad, 0) < 0);
614 igt_assert(gem_reset_status(fd_good, 0) < 0);
617 static void test_ban_ctx(void)
619 int h1,h2,h3,h4,h5,h6,h7;
620 int ctx_good, ctx_bad;
623 int active_count = 0, pending_count = 0;
624 struct local_drm_i915_reset_stats rs_bad, rs_good;
629 assert_reset_status(fd, 0, RS_NO_ERROR);
631 ctx_good = context_create(fd);
632 ctx_bad = context_create(fd);
634 assert_reset_status(fd, 0, RS_NO_ERROR);
635 assert_reset_status(fd, ctx_good, RS_NO_ERROR);
636 assert_reset_status(fd, ctx_bad, RS_NO_ERROR);
638 h1 = exec_valid(fd, ctx_bad);
640 h5 = exec_valid(fd, ctx_good);
643 assert_reset_status(fd, ctx_good, RS_NO_ERROR);
644 assert_reset_status(fd, ctx_bad, RS_NO_ERROR);
646 h2 = inject_hang(fd, ctx_bad);
649 /* Second hang will be pending for this */
652 h6 = exec_valid(fd, ctx_good);
653 h7 = exec_valid(fd, ctx_good);
656 h3 = inject_hang(fd, ctx_bad);
660 /* This second hand will count as pending */
661 assert_reset_status(fd, ctx_bad, RS_BATCH_ACTIVE);
663 h4 = exec_valid(fd, ctx_bad);
669 /* Should not happen often but sometimes hang is declared too slow
670 * due to our way of faking hang using loop */
676 printf("retrying for ban (%d)\n", retry);
679 igt_assert(h4 == -EIO);
680 assert_reset_status(fd, ctx_bad, RS_BATCH_ACTIVE);
683 assert_reset_status(fd, ctx_good, RS_BATCH_PENDING);
685 igt_assert(gem_reset_stats(fd, ctx_good, &rs_good) == 0);
686 igt_assert(gem_reset_stats(fd, ctx_bad, &rs_bad) == 0);
688 igt_assert(rs_bad.batch_active == active_count);
689 igt_assert(rs_bad.batch_pending == pending_count);
690 igt_assert(rs_good.batch_active == 0);
691 igt_assert(rs_good.batch_pending == 2);
698 h1 = exec_valid(fd, ctx_good);
702 igt_assert(context_destroy(fd, ctx_good) == 0);
703 igt_assert(context_destroy(fd, ctx_bad) == 0);
704 igt_assert(gem_reset_status(fd, ctx_good) < 0);
705 igt_assert(gem_reset_status(fd, ctx_bad) < 0);
706 igt_assert(exec_valid(fd, ctx_good) < 0);
707 igt_assert(exec_valid(fd, ctx_bad) < 0);
712 static void test_unrelated_ctx(void)
716 int ctx_guilty, ctx_unrelated;
718 fd1 = drm_open_any();
719 fd2 = drm_open_any();
720 assert_reset_status(fd1, 0, RS_NO_ERROR);
721 assert_reset_status(fd2, 0, RS_NO_ERROR);
722 ctx_guilty = context_create(fd1);
723 ctx_unrelated = context_create(fd2);
725 assert_reset_status(fd1, ctx_guilty, RS_NO_ERROR);
726 assert_reset_status(fd2, ctx_unrelated, RS_NO_ERROR);
728 h1 = inject_hang(fd1, ctx_guilty);
731 assert_reset_status(fd1, ctx_guilty, RS_BATCH_ACTIVE);
732 assert_reset_status(fd2, ctx_unrelated, RS_NO_ERROR);
734 h2 = exec_valid(fd2, ctx_unrelated);
737 assert_reset_status(fd1, ctx_guilty, RS_BATCH_ACTIVE);
738 assert_reset_status(fd2, ctx_unrelated, RS_NO_ERROR);
742 igt_assert(context_destroy(fd1, ctx_guilty) == 0);
743 igt_assert(context_destroy(fd2, ctx_unrelated) == 0);
749 static int get_reset_count(int fd, int ctx)
752 struct local_drm_i915_reset_stats rs;
754 ret = gem_reset_stats(fd, ctx, &rs);
758 return rs.reset_count;
761 static void test_close_pending_ctx(void)
768 ctx = context_create(fd);
770 assert_reset_status(fd, ctx, RS_NO_ERROR);
772 h = inject_hang(fd, ctx);
774 igt_assert(context_destroy(fd, ctx) == 0);
775 igt_assert(context_destroy(fd, ctx) == -ENOENT);
781 static void test_close_pending(void)
788 assert_reset_status(fd, 0, RS_NO_ERROR);
790 h = inject_hang(fd, 0);
797 static void exec_noop_on_each_ring(int fd, const bool reverse)
799 uint32_t batch[2] = {MI_BATCH_BUFFER_END, 0};
801 struct drm_i915_gem_execbuffer2 execbuf;
802 struct drm_i915_gem_exec_object2 exec[1];
804 handle = gem_create(fd, 4096);
805 gem_write(fd, handle, 0, batch, sizeof(batch));
807 exec[0].handle = handle;
808 exec[0].relocation_count = 0;
809 exec[0].relocs_ptr = 0;
810 exec[0].alignment = 0;
816 execbuf.buffers_ptr = (uintptr_t)exec;
817 execbuf.buffer_count = 1;
818 execbuf.batch_start_offset = 0;
819 execbuf.batch_len = 8;
820 execbuf.cliprects_ptr = 0;
821 execbuf.num_cliprects = 0;
825 i915_execbuffer2_set_context_id(execbuf, 0);
828 for (unsigned i = 0; i < NUM_RINGS; i++) {
829 const struct target_ring *ring;
831 ring = reverse ? &rings[NUM_RINGS - 1 - i] : &rings[i];
833 if (ring->present(fd)) {
834 execbuf.flags = ring->exec;
835 do_ioctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf);
839 gem_sync(fd, handle);
840 gem_close(fd, handle);
843 static void test_close_pending_fork(const bool reverse)
851 assert_reset_status(fd, 0, RS_NO_ERROR);
853 h = inject_hang(fd, 0);
858 /* Avoid helpers as we need to kill the child
859 * without any extra signal handling on behalf of
864 const int fd2 = drm_open_any();
865 igt_assert(fd2 >= 0);
867 /* The crucial component is that we schedule the same noop batch
868 * on each ring. This exercises batch_obj reference counting,
869 * when gpu is reset and ring lists are cleared.
871 exec_noop_on_each_ring(fd2, reverse);
879 /* Kill the child to reduce refcounts on
887 /* Then we just wait on hang to happen */
891 h = exec_valid(fd, 0);
899 static void test_reset_count(const bool create_ctx)
907 ctx = context_create(fd);
911 assert_reset_status(fd, ctx, RS_NO_ERROR);
913 c1 = get_reset_count(fd, ctx);
916 h = inject_hang(fd, ctx);
920 assert_reset_status(fd, ctx, RS_BATCH_ACTIVE);
921 c2 = get_reset_count(fd, ctx);
923 igt_assert(c2 == (c1 + 1));
928 c2 = get_reset_count(fd, ctx);
931 igt_assert(c2 == -EPERM);
941 context_destroy(fd, ctx);
946 static int _test_params(int fd, int ctx, uint32_t flags, uint32_t pad)
948 struct local_drm_i915_reset_stats rs;
953 rs.reset_count = rand();
954 rs.batch_active = rand();
955 rs.batch_pending = rand();
959 ret = ioctl(fd, GET_RESET_STATS_IOCTL, &rs);
960 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
968 typedef enum { root = 0, user } cap_t;
970 static void _check_param_ctx(const int fd, const int ctx, const cap_t cap)
972 const uint32_t bad = rand() + 1;
976 igt_assert(_test_params(fd, ctx, 0, 0) == 0);
978 igt_assert(_test_params(fd, ctx, 0, 0) == -EPERM);
981 igt_assert(_test_params(fd, ctx, 0, bad) == -EINVAL);
982 igt_assert(_test_params(fd, ctx, bad, 0) == -EINVAL);
983 igt_assert(_test_params(fd, ctx, bad, bad) == -EINVAL);
986 static void check_params(const int fd, const int ctx, cap_t cap)
988 igt_assert(ioctl(fd, GET_RESET_STATS_IOCTL, 0) == -1);
989 igt_assert(_test_params(fd, 0xbadbad, 0, 0) == -ENOENT);
991 _check_param_ctx(fd, ctx, cap);
994 static void _test_param(const int fd, const int ctx)
996 check_params(fd, ctx, root);
999 check_params(fd, ctx, root);
1003 check_params(fd, ctx, user);
1006 check_params(fd, ctx, root);
1011 static void test_params_ctx(void)
1015 fd = drm_open_any();
1016 igt_assert(fd >= 0);
1017 ctx = context_create(fd);
1019 _test_param(fd, ctx);
1024 static void test_params(void)
1028 fd = drm_open_any();
1029 igt_assert(fd >= 0);
1037 static bool gem_has_hw_contexts(int fd)
1039 struct local_drm_i915_gem_context_create create;
1042 memset(&create, 0, sizeof(create));
1043 ret = drmIoctl(fd, CONTEXT_CREATE_IOCTL, &create);
1046 drmIoctl(fd, CONTEXT_DESTROY_IOCTL, &create);
1053 static bool gem_has_reset_stats(int fd)
1055 struct local_drm_i915_reset_stats rs;
1058 /* Carefully set flags and pad to zero, otherwise
1061 memset(&rs, 0, sizeof(rs));
1063 ret = drmIoctl(fd, GET_RESET_STATS_IOCTL, &rs);
1067 /* If we get EPERM, we have support but did not
1069 if (ret == -1 && errno == EPERM)
1075 #define RING_HAS_CONTEXTS (current_ring->contexts(current_ring))
1076 #define RUN_CTX_TEST(...) do { igt_skip_on(RING_HAS_CONTEXTS == false); __VA_ARGS__; } while (0)
1082 igt_skip_on_simulation();
1085 bool has_reset_stats;
1086 fd = drm_open_any();
1087 devid = intel_get_drm_devid(fd);
1089 hw_contexts = gem_has_hw_contexts(fd);
1090 has_reset_stats = gem_has_reset_stats(fd);
1092 igt_require_f(has_reset_stats,
1093 "No reset stats ioctl support. Too old kernel?\n");
1096 igt_subtest("params")
1099 for (int i = 0; i < NUM_RINGS; i++) {
1102 current_ring = &rings[i];
1103 name = current_ring->name;
1106 gem_require_ring(fd, current_ring->exec);
1109 igt_require_f(intel_gen(devid) >= 4,
1110 "gen %d doesn't support reset\n", intel_gen(devid));
1112 igt_subtest_f("params-ctx-%s", name)
1113 RUN_CTX_TEST(test_params_ctx());
1115 igt_subtest_f("reset-stats-%s", name)
1118 igt_subtest_f("reset-stats-ctx-%s", name)
1119 RUN_CTX_TEST(test_rs_ctx(4, 4, 1, 2));
1121 igt_subtest_f("ban-%s", name)
1124 igt_subtest_f("ban-ctx-%s", name)
1125 RUN_CTX_TEST(test_ban_ctx());
1127 igt_subtest_f("reset-count-%s", name)
1128 test_reset_count(false);
1130 igt_subtest_f("reset-count-ctx-%s", name)
1131 RUN_CTX_TEST(test_reset_count(true));
1133 igt_subtest_f("unrelated-ctx-%s", name)
1134 RUN_CTX_TEST(test_unrelated_ctx());
1136 igt_subtest_f("close-pending-%s", name) {
1137 test_close_pending();
1138 gem_quiescent_gpu(fd);
1141 igt_subtest_f("close-pending-ctx-%s", name) {
1142 RUN_CTX_TEST(test_close_pending_ctx());
1143 gem_quiescent_gpu(fd);
1146 igt_subtest_f("close-pending-fork-%s", name) {
1147 test_close_pending_fork(true);
1148 test_close_pending_fork(false);