2 * Copyright (c) 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Mika Kuoppala <mika.kuoppala@intel.com>
38 #include <sys/ioctl.h>
43 #include "ioctl_wrappers.h"
45 #include "igt_debugfs.h"
46 #include "intel_chipset.h"
51 #define RS_BATCH_ACTIVE (1 << 0)
52 #define RS_BATCH_PENDING (1 << 1)
53 #define RS_UNKNOWN (1 << 2)
55 static uint32_t devid;
56 static bool hw_contexts;
58 struct local_drm_i915_reset_stats {
67 struct local_drm_i915_gem_context_create {
72 struct local_drm_i915_gem_context_destroy {
79 #define CONTEXT_CREATE_IOCTL DRM_IOWR(DRM_COMMAND_BASE + 0x2d, struct local_drm_i915_gem_context_create)
80 #define CONTEXT_DESTROY_IOCTL DRM_IOWR(DRM_COMMAND_BASE + 0x2e, struct local_drm_i915_gem_context_destroy)
81 #define GET_RESET_STATS_IOCTL DRM_IOWR(DRM_COMMAND_BASE + 0x32, struct local_drm_i915_reset_stats)
83 #define LOCAL_I915_EXEC_VEBOX (4 << 0)
87 static bool gem_has_render(int fd)
92 static bool has_context(const struct target_ring *ring);
94 static const struct target_ring {
96 bool (*present)(int fd);
97 bool (*contexts)(const struct target_ring *ring);
100 { I915_EXEC_RENDER, gem_has_render, has_context, "render" },
101 { I915_EXEC_BLT, gem_has_blt, has_context, "blt" },
102 { I915_EXEC_BSD, gem_has_bsd, has_context, "bsd" },
103 { LOCAL_I915_EXEC_VEBOX, gem_has_vebox, has_context, "vebox" },
106 static bool has_context(const struct target_ring *ring)
111 if(ring->exec == I915_EXEC_RENDER)
117 #define NUM_RINGS (sizeof(rings)/sizeof(struct target_ring))
119 static const struct target_ring *current_ring;
121 static uint32_t context_create(int fd)
123 struct local_drm_i915_gem_context_create create;
126 create.ctx_id = rand();
129 ret = drmIoctl(fd, CONTEXT_CREATE_IOCTL, &create);
130 igt_assert(ret == 0);
132 return create.ctx_id;
135 static int context_destroy(int fd, uint32_t ctx_id)
138 struct local_drm_i915_gem_context_destroy destroy;
140 destroy.ctx_id = ctx_id;
141 destroy.pad = rand();
143 ret = drmIoctl(fd, CONTEXT_DESTROY_IOCTL, &destroy);
150 static int gem_reset_stats(int fd, int ctx_id,
151 struct local_drm_i915_reset_stats *rs)
157 rs->reset_count = rand();
158 rs->batch_active = rand();
159 rs->batch_pending = rand();
163 ret = ioctl(fd, GET_RESET_STATS_IOCTL, rs);
164 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
172 static int gem_reset_status(int fd, int ctx_id)
175 struct local_drm_i915_reset_stats rs;
177 ret = gem_reset_stats(fd, ctx_id, &rs);
182 return RS_BATCH_ACTIVE;
183 if (rs.batch_pending)
184 return RS_BATCH_PENDING;
189 static int gem_exec(int fd, struct drm_i915_gem_execbuffer2 *execbuf)
194 DRM_IOCTL_I915_GEM_EXECBUFFER2,
203 static int exec_valid_ring(int fd, int ctx, int ring)
205 struct drm_i915_gem_execbuffer2 execbuf;
206 struct drm_i915_gem_exec_object2 exec;
209 uint32_t buf[2] = { MI_BATCH_BUFFER_END, 0 };
211 exec.handle = gem_create(fd, 4096);
212 gem_write(fd, exec.handle, 0, buf, sizeof(buf));
213 exec.relocation_count = 0;
221 execbuf.buffers_ptr = (uintptr_t)&exec;
222 execbuf.buffer_count = 1;
223 execbuf.batch_start_offset = 0;
224 execbuf.batch_len = sizeof(buf);
225 execbuf.cliprects_ptr = 0;
226 execbuf.num_cliprects = 0;
229 execbuf.flags = ring;
230 i915_execbuffer2_set_context_id(execbuf, ctx);
233 ret = gem_exec(fd, &execbuf);
240 static int exec_valid(int fd, int ctx)
242 return exec_valid_ring(fd, ctx, current_ring->exec);
245 #define BUFSIZE (4 * 1024)
246 #define ITEMS (BUFSIZE >> 2)
248 static int inject_hang_ring(int fd, int ctx, int ring, bool ignore_ban_error)
250 struct drm_i915_gem_execbuffer2 execbuf;
251 struct drm_i915_gem_exec_object2 exec;
255 unsigned cmd_len = 2;
256 enum stop_ring_flags flags;
260 if (intel_gen(devid) >= 8)
263 buf = malloc(BUFSIZE);
264 igt_assert(buf != NULL);
266 buf[0] = MI_BATCH_BUFFER_END;
269 exec.handle = gem_create(fd, BUFSIZE);
270 gem_write(fd, exec.handle, 0, buf, BUFSIZE);
271 exec.relocation_count = 0;
279 execbuf.buffers_ptr = (uintptr_t)&exec;
280 execbuf.buffer_count = 1;
281 execbuf.batch_start_offset = 0;
282 execbuf.batch_len = BUFSIZE;
283 execbuf.cliprects_ptr = 0;
284 execbuf.num_cliprects = 0;
287 execbuf.flags = ring;
288 i915_execbuffer2_set_context_id(execbuf, ctx);
291 igt_assert(gem_exec(fd, &execbuf) == 0);
293 gtt_off = exec.offset;
295 for (i = 0; i < ITEMS; i++)
298 roff = random() % (ITEMS - cmd_len - 1);
299 buf[roff] = MI_BATCH_BUFFER_START | (cmd_len - 2);
300 buf[roff + 1] = (gtt_off & 0xfffffffc) + (roff << 2);
302 buf[roff + 2] = (gtt_off & 0xffffffff00000000ull) >> 32;
304 buf[roff + cmd_len] = MI_BATCH_BUFFER_END;
306 igt_debug("loop injected at 0x%lx (off 0x%x, bo_start 0x%lx, bo_end 0x%lx)\n",
307 (long unsigned int)((roff << 2) + gtt_off),
308 roff << 2, (long unsigned int)gtt_off,
309 (long unsigned int)(gtt_off + BUFSIZE - 1));
310 gem_write(fd, exec.handle, 0, buf, BUFSIZE);
312 exec.relocation_count = 0;
320 execbuf.buffers_ptr = (uintptr_t)&exec;
321 execbuf.buffer_count = 1;
322 execbuf.batch_start_offset = 0;
323 execbuf.batch_len = BUFSIZE;
324 execbuf.cliprects_ptr = 0;
325 execbuf.num_cliprects = 0;
328 execbuf.flags = ring;
329 i915_execbuffer2_set_context_id(execbuf, ctx);
332 igt_assert(gem_exec(fd, &execbuf) == 0);
334 igt_assert(gtt_off == exec.offset);
338 flags = igt_to_stop_ring_flag(ring);
340 flags |= STOP_RING_ALLOW_BAN;
342 if (!ignore_ban_error)
343 flags |= STOP_RING_ALLOW_ERRORS;
345 igt_set_stop_rings(flags);
350 static int inject_hang(int fd, int ctx)
352 return inject_hang_ring(fd, ctx, current_ring->exec, false);
355 static int inject_hang_no_ban_error(int fd, int ctx)
357 return inject_hang_ring(fd, ctx, current_ring->exec, true);
360 static int _assert_reset_status(int fd, int ctx, int status)
364 rs = gem_reset_status(fd, ctx);
366 igt_info("reset status for %d ctx %d returned %d\n",
372 igt_info("%d:%d reset status %d differs from assumed %d\n",
373 fd, ctx, rs, status);
381 #define assert_reset_status(fd, ctx, status) \
382 igt_assert(_assert_reset_status(fd, ctx, status) == 0)
384 static void test_rs(int num_fds, int hang_index, int rs_assumed_no_hang)
390 igt_assert (num_fds <= MAX_FD);
391 igt_assert (hang_index < MAX_FD);
393 for (i = 0; i < num_fds; i++) {
394 fd[i] = drm_open_any();
398 for (i = 0; i < num_fds; i++)
399 assert_reset_status(fd[i], 0, RS_NO_ERROR);
401 for (i = 0; i < num_fds; i++) {
403 h[i] = inject_hang(fd[i], 0);
405 h[i] = exec_valid(fd[i], 0);
408 gem_sync(fd[num_fds - 1], h[num_fds - 1]);
410 for (i = 0; i < num_fds; i++) {
411 if (hang_index < 0) {
412 assert_reset_status(fd[i], 0, rs_assumed_no_hang);
417 assert_reset_status(fd[i], 0, RS_NO_ERROR);
419 assert_reset_status(fd[i], 0, RS_BATCH_ACTIVE);
421 assert_reset_status(fd[i], 0, RS_BATCH_PENDING);
424 for (i = 0; i < num_fds; i++) {
425 gem_close(fd[i], h[i]);
431 static void test_rs_ctx(int num_fds, int num_ctx, int hang_index,
436 int h[MAX_FD][MAX_CTX];
437 int ctx[MAX_FD][MAX_CTX];
439 igt_assert (num_fds <= MAX_FD);
440 igt_assert (hang_index < MAX_FD);
442 igt_assert (num_ctx <= MAX_CTX);
443 igt_assert (hang_context < MAX_CTX);
445 test_rs(num_fds, -1, RS_NO_ERROR);
447 for (i = 0; i < num_fds; i++) {
448 fd[i] = drm_open_any();
450 assert_reset_status(fd[i], 0, RS_NO_ERROR);
452 for (j = 0; j < num_ctx; j++) {
453 ctx[i][j] = context_create(fd[i]);
457 assert_reset_status(fd[i], 0, RS_NO_ERROR);
460 for (i = 0; i < num_fds; i++) {
462 assert_reset_status(fd[i], 0, RS_NO_ERROR);
464 for (j = 0; j < num_ctx; j++)
465 assert_reset_status(fd[i], ctx[i][j], RS_NO_ERROR);
467 assert_reset_status(fd[i], 0, RS_NO_ERROR);
470 for (i = 0; i < num_fds; i++) {
471 for (j = 0; j < num_ctx; j++) {
472 if (i == hang_index && j == hang_context)
473 h[i][j] = inject_hang(fd[i], ctx[i][j]);
475 h[i][j] = exec_valid(fd[i], ctx[i][j]);
479 gem_sync(fd[num_fds - 1], ctx[num_fds - 1][num_ctx - 1]);
481 for (i = 0; i < num_fds; i++)
482 assert_reset_status(fd[i], 0, RS_NO_ERROR);
484 for (i = 0; i < num_fds; i++) {
485 for (j = 0; j < num_ctx; j++) {
487 assert_reset_status(fd[i], ctx[i][j], RS_NO_ERROR);
488 if (i == hang_index && j < hang_context)
489 assert_reset_status(fd[i], ctx[i][j], RS_NO_ERROR);
490 if (i == hang_index && j == hang_context)
491 assert_reset_status(fd[i], ctx[i][j],
493 if (i == hang_index && j > hang_context)
494 assert_reset_status(fd[i], ctx[i][j],
497 assert_reset_status(fd[i], ctx[i][j],
502 for (i = 0; i < num_fds; i++) {
503 for (j = 0; j < num_ctx; j++) {
504 gem_close(fd[i], h[i][j]);
505 igt_assert(context_destroy(fd[i], ctx[i][j]) == 0);
508 assert_reset_status(fd[i], 0, RS_NO_ERROR);
514 static void test_ban(void)
516 int h1,h2,h3,h4,h5,h6,h7;
519 int active_count = 0, pending_count = 0;
520 struct local_drm_i915_reset_stats rs_bad, rs_good;
522 fd_bad = drm_open_any();
523 igt_assert(fd_bad >= 0);
525 fd_good = drm_open_any();
526 igt_assert(fd_good >= 0);
528 assert_reset_status(fd_bad, 0, RS_NO_ERROR);
529 assert_reset_status(fd_good, 0, RS_NO_ERROR);
531 h1 = exec_valid(fd_bad, 0);
533 h5 = exec_valid(fd_good, 0);
536 assert_reset_status(fd_bad, 0, RS_NO_ERROR);
537 assert_reset_status(fd_good, 0, RS_NO_ERROR);
539 h2 = inject_hang_no_ban_error(fd_bad, 0);
542 /* Second hang will be pending for this */
545 h6 = exec_valid(fd_good, 0);
546 h7 = exec_valid(fd_good, 0);
549 h3 = inject_hang_no_ban_error(fd_bad, 0);
551 gem_sync(fd_bad, h3);
553 /* This second hand will count as pending */
554 assert_reset_status(fd_bad, 0, RS_BATCH_ACTIVE);
556 h4 = exec_valid(fd_bad, 0);
558 gem_close(fd_bad, h3);
562 /* Should not happen often but sometimes hang is declared too slow
563 * due to our way of faking hang using loop */
566 gem_close(fd_bad, h3);
567 gem_close(fd_bad, h4);
569 igt_info("retrying for ban (%d)\n", retry);
572 igt_assert(h4 == -EIO);
573 assert_reset_status(fd_bad, 0, RS_BATCH_ACTIVE);
575 gem_sync(fd_good, h7);
576 assert_reset_status(fd_good, 0, RS_BATCH_PENDING);
578 igt_assert(gem_reset_stats(fd_good, 0, &rs_good) == 0);
579 igt_assert(gem_reset_stats(fd_bad, 0, &rs_bad) == 0);
581 igt_assert(rs_bad.batch_active == active_count);
582 igt_assert(rs_bad.batch_pending == pending_count);
583 igt_assert(rs_good.batch_active == 0);
584 igt_assert(rs_good.batch_pending == 2);
586 gem_close(fd_bad, h1);
587 gem_close(fd_bad, h2);
588 gem_close(fd_good, h6);
589 gem_close(fd_good, h7);
591 h1 = exec_valid(fd_good, 0);
593 gem_close(fd_good, h1);
598 igt_assert(gem_reset_status(fd_bad, 0) < 0);
599 igt_assert(gem_reset_status(fd_good, 0) < 0);
602 static void test_ban_ctx(void)
604 int h1,h2,h3,h4,h5,h6,h7;
605 int ctx_good, ctx_bad;
608 int active_count = 0, pending_count = 0;
609 struct local_drm_i915_reset_stats rs_bad, rs_good;
614 assert_reset_status(fd, 0, RS_NO_ERROR);
616 ctx_good = context_create(fd);
617 ctx_bad = context_create(fd);
619 assert_reset_status(fd, 0, RS_NO_ERROR);
620 assert_reset_status(fd, ctx_good, RS_NO_ERROR);
621 assert_reset_status(fd, ctx_bad, RS_NO_ERROR);
623 h1 = exec_valid(fd, ctx_bad);
625 h5 = exec_valid(fd, ctx_good);
628 assert_reset_status(fd, ctx_good, RS_NO_ERROR);
629 assert_reset_status(fd, ctx_bad, RS_NO_ERROR);
631 h2 = inject_hang_no_ban_error(fd, ctx_bad);
634 /* Second hang will be pending for this */
637 h6 = exec_valid(fd, ctx_good);
638 h7 = exec_valid(fd, ctx_good);
641 h3 = inject_hang_no_ban_error(fd, ctx_bad);
645 /* This second hand will count as pending */
646 assert_reset_status(fd, ctx_bad, RS_BATCH_ACTIVE);
648 h4 = exec_valid(fd, ctx_bad);
654 /* Should not happen often but sometimes hang is declared too slow
655 * due to our way of faking hang using loop */
661 igt_info("retrying for ban (%d)\n", retry);
664 igt_assert(h4 == -EIO);
665 assert_reset_status(fd, ctx_bad, RS_BATCH_ACTIVE);
668 assert_reset_status(fd, ctx_good, RS_BATCH_PENDING);
670 igt_assert(gem_reset_stats(fd, ctx_good, &rs_good) == 0);
671 igt_assert(gem_reset_stats(fd, ctx_bad, &rs_bad) == 0);
673 igt_assert(rs_bad.batch_active == active_count);
674 igt_assert(rs_bad.batch_pending == pending_count);
675 igt_assert(rs_good.batch_active == 0);
676 igt_assert(rs_good.batch_pending == 2);
683 h1 = exec_valid(fd, ctx_good);
687 igt_assert(context_destroy(fd, ctx_good) == 0);
688 igt_assert(context_destroy(fd, ctx_bad) == 0);
689 igt_assert(gem_reset_status(fd, ctx_good) < 0);
690 igt_assert(gem_reset_status(fd, ctx_bad) < 0);
691 igt_assert(exec_valid(fd, ctx_good) < 0);
692 igt_assert(exec_valid(fd, ctx_bad) < 0);
697 static void test_unrelated_ctx(void)
701 int ctx_guilty, ctx_unrelated;
703 fd1 = drm_open_any();
704 fd2 = drm_open_any();
705 assert_reset_status(fd1, 0, RS_NO_ERROR);
706 assert_reset_status(fd2, 0, RS_NO_ERROR);
707 ctx_guilty = context_create(fd1);
708 ctx_unrelated = context_create(fd2);
710 assert_reset_status(fd1, ctx_guilty, RS_NO_ERROR);
711 assert_reset_status(fd2, ctx_unrelated, RS_NO_ERROR);
713 h1 = inject_hang(fd1, ctx_guilty);
716 assert_reset_status(fd1, ctx_guilty, RS_BATCH_ACTIVE);
717 assert_reset_status(fd2, ctx_unrelated, RS_NO_ERROR);
719 h2 = exec_valid(fd2, ctx_unrelated);
722 assert_reset_status(fd1, ctx_guilty, RS_BATCH_ACTIVE);
723 assert_reset_status(fd2, ctx_unrelated, RS_NO_ERROR);
727 igt_assert(context_destroy(fd1, ctx_guilty) == 0);
728 igt_assert(context_destroy(fd2, ctx_unrelated) == 0);
734 static int get_reset_count(int fd, int ctx)
737 struct local_drm_i915_reset_stats rs;
739 ret = gem_reset_stats(fd, ctx, &rs);
743 return rs.reset_count;
746 static void test_close_pending_ctx(void)
753 ctx = context_create(fd);
755 assert_reset_status(fd, ctx, RS_NO_ERROR);
757 h = inject_hang(fd, ctx);
759 igt_assert(context_destroy(fd, ctx) == 0);
760 igt_assert(context_destroy(fd, ctx) == -ENOENT);
766 static void test_close_pending(void)
773 assert_reset_status(fd, 0, RS_NO_ERROR);
775 h = inject_hang(fd, 0);
782 static void exec_noop_on_each_ring(int fd, const bool reverse)
784 uint32_t batch[2] = {MI_BATCH_BUFFER_END, 0};
786 struct drm_i915_gem_execbuffer2 execbuf;
787 struct drm_i915_gem_exec_object2 exec[1];
789 handle = gem_create(fd, 4096);
790 gem_write(fd, handle, 0, batch, sizeof(batch));
792 exec[0].handle = handle;
793 exec[0].relocation_count = 0;
794 exec[0].relocs_ptr = 0;
795 exec[0].alignment = 0;
801 execbuf.buffers_ptr = (uintptr_t)exec;
802 execbuf.buffer_count = 1;
803 execbuf.batch_start_offset = 0;
804 execbuf.batch_len = 8;
805 execbuf.cliprects_ptr = 0;
806 execbuf.num_cliprects = 0;
810 i915_execbuffer2_set_context_id(execbuf, 0);
813 for (unsigned i = 0; i < NUM_RINGS; i++) {
814 const struct target_ring *ring;
816 ring = reverse ? &rings[NUM_RINGS - 1 - i] : &rings[i];
818 if (ring->present(fd)) {
819 execbuf.flags = ring->exec;
820 do_ioctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf);
824 gem_sync(fd, handle);
825 gem_close(fd, handle);
828 static void test_close_pending_fork(const bool reverse)
836 assert_reset_status(fd, 0, RS_NO_ERROR);
838 h = inject_hang(fd, 0);
843 /* Avoid helpers as we need to kill the child
844 * without any extra signal handling on behalf of
849 const int fd2 = drm_open_any();
850 igt_assert(fd2 >= 0);
852 /* The crucial component is that we schedule the same noop batch
853 * on each ring. This exercises batch_obj reference counting,
854 * when gpu is reset and ring lists are cleared.
856 exec_noop_on_each_ring(fd2, reverse);
864 /* Kill the child to reduce refcounts on
872 /* Then we just wait on hang to happen */
876 h = exec_valid(fd, 0);
884 static void test_reset_count(const bool create_ctx)
892 ctx = context_create(fd);
896 assert_reset_status(fd, ctx, RS_NO_ERROR);
898 c1 = get_reset_count(fd, ctx);
901 h = inject_hang(fd, ctx);
905 assert_reset_status(fd, ctx, RS_BATCH_ACTIVE);
906 c2 = get_reset_count(fd, ctx);
908 igt_assert(c2 == (c1 + 1));
913 c2 = get_reset_count(fd, ctx);
916 igt_assert(c2 == -EPERM);
926 context_destroy(fd, ctx);
931 static int _test_params(int fd, int ctx, uint32_t flags, uint32_t pad)
933 struct local_drm_i915_reset_stats rs;
938 rs.reset_count = rand();
939 rs.batch_active = rand();
940 rs.batch_pending = rand();
944 ret = ioctl(fd, GET_RESET_STATS_IOCTL, &rs);
945 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
953 typedef enum { root = 0, user } cap_t;
955 static void _check_param_ctx(const int fd, const int ctx, const cap_t cap)
957 const uint32_t bad = rand() + 1;
961 igt_assert(_test_params(fd, ctx, 0, 0) == 0);
963 igt_assert(_test_params(fd, ctx, 0, 0) == -EPERM);
966 igt_assert(_test_params(fd, ctx, 0, bad) == -EINVAL);
967 igt_assert(_test_params(fd, ctx, bad, 0) == -EINVAL);
968 igt_assert(_test_params(fd, ctx, bad, bad) == -EINVAL);
971 static void check_params(const int fd, const int ctx, cap_t cap)
973 igt_assert(ioctl(fd, GET_RESET_STATS_IOCTL, 0) == -1);
974 igt_assert(_test_params(fd, 0xbadbad, 0, 0) == -ENOENT);
976 _check_param_ctx(fd, ctx, cap);
979 static void _test_param(const int fd, const int ctx)
981 check_params(fd, ctx, root);
984 check_params(fd, ctx, root);
988 check_params(fd, ctx, user);
991 check_params(fd, ctx, root);
996 static void test_params_ctx(void)
1000 fd = drm_open_any();
1001 igt_assert(fd >= 0);
1002 ctx = context_create(fd);
1004 _test_param(fd, ctx);
1009 static void test_params(void)
1013 fd = drm_open_any();
1014 igt_assert(fd >= 0);
1022 static bool gem_has_hw_contexts(int fd)
1024 struct local_drm_i915_gem_context_create create;
1027 memset(&create, 0, sizeof(create));
1028 ret = drmIoctl(fd, CONTEXT_CREATE_IOCTL, &create);
1031 drmIoctl(fd, CONTEXT_DESTROY_IOCTL, &create);
1038 static bool gem_has_reset_stats(int fd)
1040 struct local_drm_i915_reset_stats rs;
1043 /* Carefully set flags and pad to zero, otherwise
1046 memset(&rs, 0, sizeof(rs));
1048 ret = drmIoctl(fd, GET_RESET_STATS_IOCTL, &rs);
1052 /* If we get EPERM, we have support but did not
1054 if (ret == -1 && errno == EPERM)
1060 static void check_gpu_ok(void)
1062 int retry_count = 30;
1063 enum stop_ring_flags flags;
1066 igt_debug("checking gpu state\n");
1068 while (retry_count--) {
1069 flags = igt_get_stop_rings();
1073 igt_debug("waiting previous hang to clear\n");
1077 igt_assert(flags == 0);
1079 fd = drm_open_any();
1080 gem_quiescent_gpu(fd);
1084 #define RING_HAS_CONTEXTS (current_ring->contexts(current_ring))
1085 #define RUN_TEST(...) do { check_gpu_ok(); __VA_ARGS__; check_gpu_ok(); } while (0)
1086 #define RUN_CTX_TEST(...) do { igt_skip_on(RING_HAS_CONTEXTS == false); RUN_TEST(__VA_ARGS__); } while (0)
1090 igt_skip_on_simulation();
1095 bool has_reset_stats;
1096 fd = drm_open_any();
1097 devid = intel_get_drm_devid(fd);
1099 hw_contexts = gem_has_hw_contexts(fd);
1100 has_reset_stats = gem_has_reset_stats(fd);
1104 igt_require_f(has_reset_stats,
1105 "No reset stats ioctl support. Too old kernel?\n");
1108 igt_subtest("params")
1111 for (int i = 0; i < NUM_RINGS; i++) {
1114 current_ring = &rings[i];
1115 name = current_ring->name;
1118 int fd = drm_open_any();
1119 gem_require_ring(fd, current_ring->exec);
1124 igt_require_f(intel_gen(devid) >= 4,
1125 "gen %d doesn't support reset\n", intel_gen(devid));
1127 igt_subtest_f("params-ctx-%s", name)
1128 RUN_CTX_TEST(test_params_ctx());
1130 igt_subtest_f("reset-stats-%s", name)
1131 RUN_TEST(test_rs(4, 1, 0));
1133 igt_subtest_f("reset-stats-ctx-%s", name)
1134 RUN_CTX_TEST(test_rs_ctx(4, 4, 1, 2));
1136 igt_subtest_f("ban-%s", name)
1137 RUN_TEST(test_ban());
1139 igt_subtest_f("ban-ctx-%s", name)
1140 RUN_CTX_TEST(test_ban_ctx());
1142 igt_subtest_f("reset-count-%s", name)
1143 RUN_TEST(test_reset_count(false));
1145 igt_subtest_f("reset-count-ctx-%s", name)
1146 RUN_CTX_TEST(test_reset_count(true));
1148 igt_subtest_f("unrelated-ctx-%s", name)
1149 RUN_CTX_TEST(test_unrelated_ctx());
1151 igt_subtest_f("close-pending-%s", name)
1152 RUN_TEST(test_close_pending());
1154 igt_subtest_f("close-pending-ctx-%s", name)
1155 RUN_CTX_TEST(test_close_pending_ctx());
1157 igt_subtest_f("close-pending-fork-%s", name)
1158 RUN_TEST(test_close_pending_fork(false));
1160 igt_subtest_f("close-pending-fork-reverse-%s", name)
1161 RUN_TEST(test_close_pending_fork(true));