tests/gem_pipe_control_store_loop.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Daniel Vetter <daniel.vetter@ffwll.ch> (based on gem_storedw_*.c)
  25  *
  26  */
  27
  28 /*
  29  * Testcase: (TLB-)Coherency of pipe_control QW writes
  30  *
  31  * Writes a counter-value into an always newly allocated target bo (by disabling
  32  * buffer reuse). Decently trashes on tlb inconsistencies, too.
  33  */
  34 #include <stdlib.h>
  35 #include <stdio.h>
  36 #include <string.h>
  37 #include <assert.h>
  38 #include <fcntl.h>
  39 #include <inttypes.h>
  40 #include <errno.h>
  41 #include <sys/stat.h>
  42 #include <sys/time.h>
  43 #include "drm.h"
  44 #include "i915_drm.h"
  45 #include "drmtest.h"
  46 #include "intel_bufmgr.h"
  47 #include "intel_batchbuffer.h"
  48 #include "intel_gpu_tools.h"
  49
  50 static drm_intel_bufmgr *bufmgr;
  51 struct intel_batchbuffer *batch;
  52 uint32_t devid;
  53
  54 #define GFX_OP_PIPE_CONTROL     ((0x3<<29)|(0x3<<27)|(0x2<<24)|2)
  55 #define   PIPE_CONTROL_WRITE_IMMEDIATE  (1<<14)
  56 #define   PIPE_CONTROL_WRITE_TIMESTAMP  (3<<14)
  57 #define   PIPE_CONTROL_DEPTH_STALL (1<<13)
  58 #define   PIPE_CONTROL_WC_FLUSH (1<<12)
  59 #define   PIPE_CONTROL_IS_FLUSH (1<<11) /* MBZ on Ironlake */
  60 #define   PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */
  61 #define   PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
  62 #define   PIPE_CONTROL_CS_STALL (1<<20)
  63 #define   PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
  64
  65 /* Like the store dword test, but we create new command buffers each time */
  66 static void
  67 store_pipe_control_loop(void)
  68 {
  69         int i, val = 0;
  70         uint32_t *buf;
  71         drm_intel_bo *target_bo;
  72
  73         for (i = 0; i < 0x10000; i++) {
  74                 /* we want to check tlb consistency of the pipe_control target,
  75                  * so get a new buffer every time around */
  76                 target_bo = drm_intel_bo_alloc(bufmgr, "target bo", 4096, 4096);
  77                 if (!target_bo) {
  78                         fprintf(stderr, "failed to alloc target buffer\n");
  79                         exit(-1);
  80                 }
  81
  82                 /* gem_storedw_batches_loop.c is a bit overenthusiastic with
  83                  * creating new batchbuffers - with buffer reuse disabled, the
  84                  * support code will do that for us. */
  85                 if (intel_gen(devid) >= 6) {
  86                         /* work-around hw issue, see intel_emit_post_sync_nonzero_flush
  87                          * in mesa sources. */
  88                         BEGIN_BATCH(4);
  89                         OUT_BATCH(GFX_OP_PIPE_CONTROL);
  90                         OUT_BATCH(PIPE_CONTROL_CS_STALL |
  91                              PIPE_CONTROL_STALL_AT_SCOREBOARD);
  92                         OUT_BATCH(0); /* address */
  93                         OUT_BATCH(0); /* write data */
  94                         ADVANCE_BATCH();
  95
  96                         BEGIN_BATCH(4);
  97                         OUT_BATCH(GFX_OP_PIPE_CONTROL);
  98                         OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
  99                         OUT_RELOC(target_bo,
 100                              I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 101                              PIPE_CONTROL_GLOBAL_GTT);
 102                         OUT_BATCH(val); /* write data */
 103                         ADVANCE_BATCH();
 104                 } else if (intel_gen(devid) >= 4) {
 105                         BEGIN_BATCH(4);
 106                         OUT_BATCH(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_WC_FLUSH |
 107                                         PIPE_CONTROL_TC_FLUSH |
 108                                         PIPE_CONTROL_WRITE_IMMEDIATE | 2);
 109                         OUT_RELOC(target_bo,
 110                                 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 111                                 PIPE_CONTROL_GLOBAL_GTT);
 112                         OUT_BATCH(val);
 113                         OUT_BATCH(0xdeadbeef);
 114                         ADVANCE_BATCH();
 115                 }
 116
 117                 intel_batchbuffer_flush_on_ring(batch, 0);
 118
 119                 drm_intel_bo_map(target_bo, 1);
 120
 121                 buf = target_bo->virtual;
 122                 if (buf[0] != val) {
 123                         fprintf(stderr,
 124                                 "value mismatch: cur 0x%08x, stored 0x%08x\n",
 125                                 buf[0], val);
 126                         exit(-1);
 127                 }
 128                 buf[0] = 0; /* let batch write it again */
 129                 drm_intel_bo_unmap(target_bo);
 130
 131                 drm_intel_bo_unreference(target_bo);
 132
 133                 val++;
 134         }
 135
 136         printf("completed %d writes successfully\n", i);
 137 }
 138
 139 int main(int argc, char **argv)
 140 {
 141         int fd;
 142
 143         if (argc != 1) {
 144                 fprintf(stderr, "usage: %s\n", argv[0]);
 145                 exit(-1);
 146         }
 147
 148         fd = drm_open_any();
 149         devid = intel_get_drm_devid(fd);
 150
 151         bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
 152         if (!bufmgr) {
 153                 fprintf(stderr, "failed to init libdrm\n");
 154                 exit(-1);
 155         }
 156
 157         if (IS_GEN2(devid) || IS_GEN3(devid)) {
 158                 fprintf(stderr, "no pipe_control on gen2/3\n");
 159                 return 77;
 160         }
 161         if (devid == PCI_CHIP_I965_G) {
 162                 fprintf(stderr, "pipe_control totally broken on i965\n");
 163                 return 77;
 164         }
 165         /* IMPORTANT: No call to
 166          * drm_intel_bufmgr_gem_enable_reuse(bufmgr);
 167          * here because we wan't to have fresh buffers (to trash the tlb)
 168          * every time! */
 169
 170         batch = intel_batchbuffer_alloc(bufmgr, devid);
 171         if (!batch) {
 172                 fprintf(stderr, "failed to create batch buffer\n");
 173                 exit(-1);
 174         }
 175
 176         store_pipe_control_loop();
 177
 178         intel_batchbuffer_free(batch);
 179         drm_intel_bufmgr_destroy(bufmgr);
 180
 181         close(fd);
 182
 183         return 0;
 184 }