tests/gem_pipe_control_store_loop.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Daniel Vetter <daniel.vetter@ffwll.ch> (based on gem_storedw_*.c)
  25  *
  26  */
  27
  28 /*
  29  * Testcase: (TLB-)Coherency of pipe_control QW writes
  30  *
  31  * Writes a counter-value into an always newly allocated target bo (by disabling
  32  * buffer reuse). Decently trashes on tlb inconsistencies, too.
  33  */
  34 #include <stdlib.h>
  35 #include <stdio.h>
  36 #include <string.h>
  37 #include <fcntl.h>
  38 #include <inttypes.h>
  39 #include <errno.h>
  40 #include <sys/stat.h>
  41 #include <sys/time.h>
  42 #include "drm.h"
  43 #include "i915_drm.h"
  44 #include "drmtest.h"
  45 #include "intel_bufmgr.h"
  46 #include "intel_batchbuffer.h"
  47 #include "intel_gpu_tools.h"
  48
  49 static drm_intel_bufmgr *bufmgr;
  50 struct intel_batchbuffer *batch;
  51 uint32_t devid;
  52
  53 #define GFX_OP_PIPE_CONTROL     ((0x3<<29)|(0x3<<27)|(0x2<<24)|2)
  54 #define   PIPE_CONTROL_WRITE_IMMEDIATE  (1<<14)
  55 #define   PIPE_CONTROL_WRITE_TIMESTAMP  (3<<14)
  56 #define   PIPE_CONTROL_DEPTH_STALL (1<<13)
  57 #define   PIPE_CONTROL_WC_FLUSH (1<<12)
  58 #define   PIPE_CONTROL_IS_FLUSH (1<<11) /* MBZ on Ironlake */
  59 #define   PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */
  60 #define   PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
  61 #define   PIPE_CONTROL_CS_STALL (1<<20)
  62 #define   PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
  63
  64 /* Like the store dword test, but we create new command buffers each time */
  65 static void
  66 store_pipe_control_loop(bool preuse_buffer)
  67 {
  68         int i, val = 0;
  69         uint32_t *buf;
  70         drm_intel_bo *target_bo;
  71
  72         for (i = 0; i < SLOW_QUICK(0x10000, 4); i++) {
  73                 /* we want to check tlb consistency of the pipe_control target,
  74                  * so get a new buffer every time around */
  75                 target_bo = drm_intel_bo_alloc(bufmgr, "target bo", 4096, 4096);
  76                 igt_assert(target_bo);
  77
  78                 if (preuse_buffer) {
  79                         COLOR_BLIT_COPY_BATCH_START(devid, 0);
  80                         OUT_BATCH((3 << 24) | (0xf0 << 16) | 64);
  81                         OUT_BATCH(0);
  82                         OUT_BATCH(1 << 16 | 1);
  83
  84                         /*
  85                          * IMPORTANT: We need to preuse the buffer in a
  86                          * different domain than what the pipe control write
  87                          * (and kernel wa) uses!
  88                          */
  89                         OUT_RELOC(target_bo,
  90                              I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
  91                              0);
  92                         BLIT_RELOC_UDW(devid);
  93                         OUT_BATCH(0xdeadbeef);
  94                         ADVANCE_BATCH();
  95
  96                         intel_batchbuffer_flush(batch);
  97                         igt_assert(target_bo->offset != 0);
  98                 } else
  99                         igt_assert(target_bo->offset == 0);
 100
 101                 /* gem_storedw_batches_loop.c is a bit overenthusiastic with
 102                  * creating new batchbuffers - with buffer reuse disabled, the
 103                  * support code will do that for us. */
 104                 if (intel_gen(devid) >= 8) {
 105                         BEGIN_BATCH(5);
 106                         OUT_BATCH(GFX_OP_PIPE_CONTROL + 1);
 107                         OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
 108                         OUT_RELOC(target_bo,
 109                              I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 110                              PIPE_CONTROL_GLOBAL_GTT);
 111                         BLIT_RELOC_UDW(devid);
 112                         OUT_BATCH(val); /* write data */
 113                         ADVANCE_BATCH();
 114
 115                 } else if (intel_gen(devid) >= 6) {
 116                         /* work-around hw issue, see intel_emit_post_sync_nonzero_flush
 117                          * in mesa sources. */
 118                         BEGIN_BATCH(4);
 119                         OUT_BATCH(GFX_OP_PIPE_CONTROL);
 120                         OUT_BATCH(PIPE_CONTROL_CS_STALL |
 121                              PIPE_CONTROL_STALL_AT_SCOREBOARD);
 122                         OUT_BATCH(0); /* address */
 123                         OUT_BATCH(0); /* write data */
 124                         ADVANCE_BATCH();
 125
 126                         BEGIN_BATCH(4);
 127                         OUT_BATCH(GFX_OP_PIPE_CONTROL);
 128                         OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
 129                         OUT_RELOC(target_bo,
 130                              I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 131                              PIPE_CONTROL_GLOBAL_GTT);
 132                         OUT_BATCH(val); /* write data */
 133                         ADVANCE_BATCH();
 134                 } else if (intel_gen(devid) >= 4) {
 135                         BEGIN_BATCH(4);
 136                         OUT_BATCH(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_WC_FLUSH |
 137                                         PIPE_CONTROL_TC_FLUSH |
 138                                         PIPE_CONTROL_WRITE_IMMEDIATE | 2);
 139                         OUT_RELOC(target_bo,
 140                                 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 141                                 PIPE_CONTROL_GLOBAL_GTT);
 142                         OUT_BATCH(val);
 143                         OUT_BATCH(0xdeadbeef);
 144                         ADVANCE_BATCH();
 145                 }
 146
 147                 intel_batchbuffer_flush_on_ring(batch, 0);
 148
 149                 drm_intel_bo_map(target_bo, 1);
 150
 151                 buf = target_bo->virtual;
 152                 igt_assert(buf[0] == val);
 153
 154                 drm_intel_bo_unmap(target_bo);
 155                 /* Make doublesure that this buffer won't get reused. */
 156                 drm_intel_bo_disable_reuse(target_bo);
 157                 drm_intel_bo_unreference(target_bo);
 158
 159                 val++;
 160         }
 161 }
 162
 163 int fd;
 164
 165 igt_main
 166 {
 167         igt_fixture {
 168                 fd = drm_open_any();
 169                 devid = intel_get_drm_devid(fd);
 170
 171                 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
 172                 igt_assert(bufmgr);
 173
 174                 igt_skip_on(IS_GEN2(devid) || IS_GEN3(devid));
 175                 igt_skip_on(devid == PCI_CHIP_I965_G); /* has totally broken pipe control */
 176
 177                 /* IMPORTANT: No call to
 178                  * drm_intel_bufmgr_gem_enable_reuse(bufmgr);
 179                  * here because we wan't to have fresh buffers (to trash the tlb)
 180                  * every time! */
 181
 182                 batch = intel_batchbuffer_alloc(bufmgr, devid);
 183                 igt_assert(batch);
 184         }
 185
 186         igt_subtest("fresh-buffer")
 187                 store_pipe_control_loop(false);
 188
 189         igt_subtest("reused-buffer")
 190                 store_pipe_control_loop(true);
 191
 192         igt_fixture {
 193                 intel_batchbuffer_free(batch);
 194                 drm_intel_bufmgr_destroy(bufmgr);
 195
 196                 close(fd);
 197         }
 198 }