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24 * Daniel Vetter <daniel.vetter@ffwll.ch> (based on gem_storedw_*.c)
29 * Testcase: (TLB-)Coherency of pipe_control QW writes
31 * Writes a counter-value into an always newly allocated target bo (by disabling
32 * buffer reuse). Decently trashes on tlb inconsistencies, too.
45 #include "intel_bufmgr.h"
46 #include "intel_batchbuffer.h"
47 #include "intel_gpu_tools.h"
49 static drm_intel_bufmgr *bufmgr;
50 struct intel_batchbuffer *batch;
53 #define GFX_OP_PIPE_CONTROL ((0x3<<29)|(0x3<<27)|(0x2<<24)|2)
54 #define PIPE_CONTROL_WRITE_IMMEDIATE (1<<14)
55 #define PIPE_CONTROL_WRITE_TIMESTAMP (3<<14)
56 #define PIPE_CONTROL_DEPTH_STALL (1<<13)
57 #define PIPE_CONTROL_WC_FLUSH (1<<12)
58 #define PIPE_CONTROL_IS_FLUSH (1<<11) /* MBZ on Ironlake */
59 #define PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */
60 #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
61 #define PIPE_CONTROL_CS_STALL (1<<20)
62 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
64 /* Like the store dword test, but we create new command buffers each time */
66 store_pipe_control_loop(void)
70 drm_intel_bo *target_bo;
72 for (i = 0; i < SLOW_QUICK(0x10000, 4); i++) {
73 /* we want to check tlb consistency of the pipe_control target,
74 * so get a new buffer every time around */
75 target_bo = drm_intel_bo_alloc(bufmgr, "target bo", 4096, 4096);
77 fprintf(stderr, "failed to alloc target buffer\n");
81 /* gem_storedw_batches_loop.c is a bit overenthusiastic with
82 * creating new batchbuffers - with buffer reuse disabled, the
83 * support code will do that for us. */
84 if (intel_gen(devid) >= 6) {
85 /* work-around hw issue, see intel_emit_post_sync_nonzero_flush
88 OUT_BATCH(GFX_OP_PIPE_CONTROL);
89 OUT_BATCH(PIPE_CONTROL_CS_STALL |
90 PIPE_CONTROL_STALL_AT_SCOREBOARD);
91 OUT_BATCH(0); /* address */
92 OUT_BATCH(0); /* write data */
96 OUT_BATCH(GFX_OP_PIPE_CONTROL);
97 OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
99 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
100 PIPE_CONTROL_GLOBAL_GTT);
101 OUT_BATCH(val); /* write data */
103 } else if (intel_gen(devid) >= 4) {
105 OUT_BATCH(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_WC_FLUSH |
106 PIPE_CONTROL_TC_FLUSH |
107 PIPE_CONTROL_WRITE_IMMEDIATE | 2);
109 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
110 PIPE_CONTROL_GLOBAL_GTT);
112 OUT_BATCH(0xdeadbeef);
116 intel_batchbuffer_flush_on_ring(batch, 0);
118 drm_intel_bo_map(target_bo, 1);
120 buf = target_bo->virtual;
123 "value mismatch: cur 0x%08x, stored 0x%08x\n",
127 buf[0] = 0; /* let batch write it again */
128 drm_intel_bo_unmap(target_bo);
130 drm_intel_bo_unreference(target_bo);
135 printf("completed %d writes successfully\n", i);
138 int main(int argc, char **argv)
143 fprintf(stderr, "usage: %s\n", argv[0]);
148 devid = intel_get_drm_devid(fd);
150 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
152 fprintf(stderr, "failed to init libdrm\n");
156 if (IS_GEN2(devid) || IS_GEN3(devid)) {
157 fprintf(stderr, "no pipe_control on gen2/3\n");
160 if (devid == PCI_CHIP_I965_G) {
161 fprintf(stderr, "pipe_control totally broken on i965\n");
164 /* IMPORTANT: No call to
165 * drm_intel_bufmgr_gem_enable_reuse(bufmgr);
166 * here because we wan't to have fresh buffers (to trash the tlb)
169 batch = intel_batchbuffer_alloc(bufmgr, devid);
171 fprintf(stderr, "failed to create batch buffer\n");
175 store_pipe_control_loop();
177 intel_batchbuffer_free(batch);
178 drm_intel_bufmgr_destroy(bufmgr);