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24 * Daniel Vetter <daniel.vetter@ffwll.ch> (based on gem_storedw_*.c)
29 * Testcase: (TLB-)Coherency of pipe_control QW writes
31 * Writes a counter-value into an always newly allocated target bo (by disabling
32 * buffer reuse). Decently trashes on tlb inconsistencies, too.
45 #include "intel_bufmgr.h"
46 #include "intel_batchbuffer.h"
47 #include "intel_gpu_tools.h"
49 static drm_intel_bufmgr *bufmgr;
50 struct intel_batchbuffer *batch;
53 #define GFX_OP_PIPE_CONTROL ((0x3<<29)|(0x3<<27)|(0x2<<24)|2)
54 #define PIPE_CONTROL_WRITE_IMMEDIATE (1<<14)
55 #define PIPE_CONTROL_WRITE_TIMESTAMP (3<<14)
56 #define PIPE_CONTROL_DEPTH_STALL (1<<13)
57 #define PIPE_CONTROL_WC_FLUSH (1<<12)
58 #define PIPE_CONTROL_IS_FLUSH (1<<11) /* MBZ on Ironlake */
59 #define PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */
60 #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
61 #define PIPE_CONTROL_CS_STALL (1<<20)
62 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
64 /* Like the store dword test, but we create new command buffers each time */
66 store_pipe_control_loop(bool preuse_buffer)
70 drm_intel_bo *target_bo;
72 for (i = 0; i < SLOW_QUICK(0x10000, 4); i++) {
73 /* we want to check tlb consistency of the pipe_control target,
74 * so get a new buffer every time around */
75 target_bo = drm_intel_bo_alloc(bufmgr, "target bo", 4096, 4096);
77 fprintf(stderr, "failed to alloc target buffer\n");
83 OUT_BATCH(XY_COLOR_BLT_CMD | COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB);
84 OUT_BATCH((3 << 24) | (0xf0 << 16) | 64);
86 OUT_BATCH(1 << 16 | 1);
89 * IMPORTANT: We need to preuse the buffer in a
90 * different domain than what the pipe control write
91 * (and kernel wa) uses!
94 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
96 OUT_BATCH(0xdeadbeef);
99 intel_batchbuffer_flush(batch);
100 igt_assert(target_bo->offset != 0);
102 igt_assert(target_bo->offset == 0);
104 /* gem_storedw_batches_loop.c is a bit overenthusiastic with
105 * creating new batchbuffers - with buffer reuse disabled, the
106 * support code will do that for us. */
107 if (intel_gen(devid) >= 6) {
108 /* work-around hw issue, see intel_emit_post_sync_nonzero_flush
109 * in mesa sources. */
111 OUT_BATCH(GFX_OP_PIPE_CONTROL);
112 OUT_BATCH(PIPE_CONTROL_CS_STALL |
113 PIPE_CONTROL_STALL_AT_SCOREBOARD);
114 OUT_BATCH(0); /* address */
115 OUT_BATCH(0); /* write data */
119 OUT_BATCH(GFX_OP_PIPE_CONTROL);
120 OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
122 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
123 PIPE_CONTROL_GLOBAL_GTT);
124 OUT_BATCH(val); /* write data */
126 } else if (intel_gen(devid) >= 4) {
128 OUT_BATCH(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_WC_FLUSH |
129 PIPE_CONTROL_TC_FLUSH |
130 PIPE_CONTROL_WRITE_IMMEDIATE | 2);
132 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
133 PIPE_CONTROL_GLOBAL_GTT);
135 OUT_BATCH(0xdeadbeef);
139 intel_batchbuffer_flush_on_ring(batch, 0);
141 drm_intel_bo_map(target_bo, 1);
143 buf = target_bo->virtual;
144 igt_assert(buf[0] == val);
146 drm_intel_bo_unmap(target_bo);
147 /* Make doublesure that this buffer won't get reused. */
148 drm_intel_bo_disable_reuse(target_bo);
149 drm_intel_bo_unreference(target_bo);
157 int main(int argc, char **argv)
159 igt_subtest_init(argc, argv);
163 devid = intel_get_drm_devid(fd);
165 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
168 igt_skip_on(IS_GEN2(devid) || IS_GEN3(devid));
169 igt_skip_on(devid == PCI_CHIP_I965_G); /* has totally broken pipe control */
171 /* IMPORTANT: No call to
172 * drm_intel_bufmgr_gem_enable_reuse(bufmgr);
173 * here because we wan't to have fresh buffers (to trash the tlb)
176 batch = intel_batchbuffer_alloc(bufmgr, devid);
180 igt_subtest("fresh-buffer")
181 store_pipe_control_loop(false);
183 igt_subtest("reused-buffer")
184 store_pipe_control_loop(true);
187 intel_batchbuffer_free(batch);
188 drm_intel_bufmgr_destroy(bufmgr);