2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Vetter <daniel.vetter@ffwll.ch> (based on gem_storedw_*.c)
29 * Testcase: (TLB-)Coherency of pipe_control QW writes
31 * Writes a counter-value into an always newly allocated target bo (by disabling
32 * buffer reuse). Decently trashes on tlb inconsistencies, too.
46 #include "intel_bufmgr.h"
47 #include "intel_batchbuffer.h"
48 #include "intel_gpu_tools.h"
50 static drm_intel_bufmgr *bufmgr;
51 struct intel_batchbuffer *batch;
54 #define GFX_OP_PIPE_CONTROL ((0x3<<29)|(0x3<<27)|(0x2<<24)|2)
55 #define PIPE_CONTROL_WRITE_IMMEDIATE (1<<14)
56 #define PIPE_CONTROL_WRITE_TIMESTAMP (3<<14)
57 #define PIPE_CONTROL_DEPTH_STALL (1<<13)
58 #define PIPE_CONTROL_WC_FLUSH (1<<12)
59 #define PIPE_CONTROL_IS_FLUSH (1<<11) /* MBZ on Ironlake */
60 #define PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */
61 #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
62 #define PIPE_CONTROL_CS_STALL (1<<20)
63 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
65 /* Like the store dword test, but we create new command buffers each time */
67 store_pipe_control_loop(void)
71 drm_intel_bo *target_bo;
73 for (i = 0; i < 0x10000; i++) {
74 /* we want to check tlb consistency of the pipe_control target,
75 * so get a new buffer every time around */
76 target_bo = drm_intel_bo_alloc(bufmgr, "target bo", 4096, 4096);
78 fprintf(stderr, "failed to alloc target buffer\n");
82 /* gem_storedw_batches_loop.c is a bit overenthusiastic with
83 * creating new batchbuffers - with buffer reuse disabled, the
84 * support code will do that for us. */
85 if (intel_gen(devid) >= 6) {
86 /* work-around hw issue, see intel_emit_post_sync_nonzero_flush
89 OUT_BATCH(GFX_OP_PIPE_CONTROL);
90 OUT_BATCH(PIPE_CONTROL_CS_STALL |
91 PIPE_CONTROL_STALL_AT_SCOREBOARD);
92 OUT_BATCH(0); /* address */
93 OUT_BATCH(0); /* write data */
97 OUT_BATCH(GFX_OP_PIPE_CONTROL);
98 OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
100 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
101 PIPE_CONTROL_GLOBAL_GTT);
102 OUT_BATCH(val); /* write data */
104 } else if (intel_gen(devid) >= 4) {
106 OUT_BATCH(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_WC_FLUSH |
107 PIPE_CONTROL_TC_FLUSH |
108 PIPE_CONTROL_WRITE_IMMEDIATE | 2);
110 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
111 PIPE_CONTROL_GLOBAL_GTT);
113 OUT_BATCH(0xdeadbeef);
117 intel_batchbuffer_flush_on_ring(batch, 0);
119 drm_intel_bo_map(target_bo, 1);
121 buf = target_bo->virtual;
124 "value mismatch: cur 0x%08x, stored 0x%08x\n",
126 buf[0] = 0; /* let batch write it again */
127 drm_intel_bo_unmap(target_bo);
129 drm_intel_bo_unreference(target_bo);
134 printf("completed %d writes successfully\n", i);
137 int main(int argc, char **argv)
142 fprintf(stderr, "usage: %s\n", argv[0]);
147 devid = intel_get_drm_devid(fd);
149 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
151 fprintf(stderr, "failed to init libdrm\n");
155 if (IS_GEN2(devid) || IS_GEN3(devid)) {
156 fprintf(stderr, "no pipe_control on gen2/3\n");
159 /* IMPORTANT: No call to
160 * drm_intel_bufmgr_gem_enable_reuse(bufmgr);
161 * here because we wan't to have fresh buffers (to trash the tlb)
164 batch = intel_batchbuffer_alloc(bufmgr, devid);
166 fprintf(stderr, "failed to create batch buffer\n");
170 store_pipe_control_loop();
172 intel_batchbuffer_free(batch);
173 drm_intel_bufmgr_destroy(bufmgr);