2 * Copyright © 20013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Chris Wilson <chris@chris-wilson.co.uk>
28 /* Exercises pinning of small bo */
42 #include "intel_chipset.h"
43 #include "intel_gpu_tools.h"
45 #define COPY_BLT_CMD (2<<29|0x53<<22|0x6)
46 #define BLT_WRITE_ALPHA (1<<21)
47 #define BLT_WRITE_RGB (1<<20)
49 static void exec(int fd, uint32_t handle, uint32_t offset)
51 struct drm_i915_gem_execbuffer2 execbuf;
52 struct drm_i915_gem_exec_object2 gem_exec[1];
53 struct drm_i915_gem_relocation_entry gem_reloc[1];
55 gem_reloc[0].offset = 1024;
56 gem_reloc[0].delta = 0;
57 gem_reloc[0].target_handle = handle;
58 gem_reloc[0].read_domains = I915_GEM_DOMAIN_RENDER;
59 gem_reloc[0].write_domain = 0;
60 gem_reloc[0].presumed_offset = 0;
62 gem_exec[0].handle = handle;
63 gem_exec[0].relocation_count = 1;
64 gem_exec[0].relocs_ptr = (uintptr_t) gem_reloc;
65 gem_exec[0].alignment = 0;
66 gem_exec[0].offset = 0;
67 gem_exec[0].flags = 0;
68 gem_exec[0].rsvd1 = 0;
69 gem_exec[0].rsvd2 = 0;
71 execbuf.buffers_ptr = (uintptr_t)gem_exec;
72 execbuf.buffer_count = 1;
73 execbuf.batch_start_offset = 0;
74 execbuf.batch_len = 8;
75 execbuf.cliprects_ptr = 0;
76 execbuf.num_cliprects = 0;
80 i915_execbuffer2_set_context_id(execbuf, 0);
83 do_or_die(drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf));
84 assert(gem_exec[0].offset == offset);
87 static int gem_linear_blt(uint32_t *batch,
91 struct drm_i915_gem_relocation_entry *reloc)
95 b[0] = COPY_BLT_CMD | BLT_WRITE_ALPHA | BLT_WRITE_RGB;
96 b[1] = 0x66 << 16 | 1 << 25 | 1 << 24 | (4*1024);
98 b[3] = (length / (4*1024)) << 16 | 1024;
100 reloc->offset = (b-batch+4) * sizeof(uint32_t);
102 reloc->target_handle = dst;
103 reloc->read_domains = I915_GEM_DOMAIN_RENDER;
104 reloc->write_domain = I915_GEM_DOMAIN_RENDER;
105 reloc->presumed_offset = 0;
111 reloc->offset = (b-batch+7) * sizeof(uint32_t);
113 reloc->target_handle = src;
114 reloc->read_domains = I915_GEM_DOMAIN_RENDER;
115 reloc->write_domain = 0;
116 reloc->presumed_offset = 0;
121 b[0] = MI_BATCH_BUFFER_END;
124 return (b+2 - batch) * sizeof(uint32_t);
127 static void make_busy(int fd, uint32_t handle)
129 struct drm_i915_gem_execbuffer2 execbuf;
130 struct drm_i915_gem_exec_object2 obj[2];
131 struct drm_i915_gem_relocation_entry reloc[2];
136 tmp = gem_create(fd, 1024*1024);
139 obj[0].relocation_count = 0;
140 obj[0].relocs_ptr = 0;
141 obj[0].alignment = 0;
147 obj[1].handle = handle;
148 obj[1].relocation_count = 2;
149 obj[1].relocs_ptr = (uintptr_t) reloc;
150 obj[1].alignment = 0;
156 execbuf.buffers_ptr = (uintptr_t)obj;
157 execbuf.buffer_count = 2;
158 execbuf.batch_start_offset = 0;
159 execbuf.batch_len = gem_linear_blt(batch, tmp, tmp, 1024*1024,reloc);
160 execbuf.cliprects_ptr = 0;
161 execbuf.num_cliprects = 0;
165 if (HAS_BLT_RING(intel_get_drm_devid(fd)))
166 execbuf.flags |= I915_EXEC_BLT;
167 i915_execbuffer2_set_context_id(execbuf, 0);
170 gem_write(fd, handle, 0, batch, execbuf.batch_len);
171 for (count = 0; count < 10; count++)
172 do_or_die(drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf));
176 static int test_can_pin(int fd)
178 struct drm_i915_gem_pin pin;
181 pin.handle = gem_create(fd, 4096);;
183 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_PIN, &pin);
184 gem_close(fd, pin.handle);
189 static uint32_t gem_pin(int fd, int handle, int alignment)
191 struct drm_i915_gem_pin pin;
194 pin.alignment = alignment;
195 do_ioctl(fd, DRM_IOCTL_I915_GEM_PIN, &pin);
199 int main(int argc, char **argv)
201 const uint32_t batch[2] = {MI_BATCH_BUFFER_END};
202 struct timeval start, now;
203 uint32_t *handle, *offset;
208 if (!test_can_pin(fd))
211 handle = malloc(sizeof(uint32_t)*100);
212 offset = malloc(sizeof(uint32_t)*100);
214 /* Race creation/use against interrupts */
215 drmtest_fork_signal_helper();
216 gettimeofday(&start, NULL);
218 for (i = 0; i < 100; i++) {
221 handle[i] = gem_create(fd, 4096);
222 offset[i] = gem_pin(fd, handle[i], 0);
224 gem_write(fd, handle[i], 0, batch, sizeof(batch));
226 /* try to pin an anidle bo */
227 handle[i] = gem_create(fd, 4096);
228 make_busy(fd, handle[i]);
229 offset[i] = gem_pin(fd, handle[i], 256*1024);
231 assert((offset[i] & (256*1024-1)) == 0);
232 gem_write(fd, handle[i], 0, batch, sizeof(batch));
235 for (i = 0; i < 1000; i++) {
236 int j = rand() % 100;
237 exec(fd, handle[j], offset[j]);
239 for (i = 0; i < 100; i++)
240 gem_close(fd, handle[i]);
241 gettimeofday(&now, NULL);
242 } while ((now.tv_sec - start.tv_sec)*1000 + (now.tv_usec - start.tv_usec) / 1000 < 10000);
243 drmtest_stop_signal_helper();