2 * Copyright © 20013 Intel Corporation
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6 * to deal in the Software without restriction, including without limitation
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11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Chris Wilson <chris@chris-wilson.co.uk>
28 /* Exercises pinning of small bo */
41 #include "ioctl_wrappers.h"
43 #include "intel_chipset.h"
47 #define COPY_BLT_CMD (2<<29|0x53<<22|0x6)
48 #define BLT_WRITE_ALPHA (1<<21)
49 #define BLT_WRITE_RGB (1<<20)
51 static void exec(int fd, uint32_t handle, uint32_t offset)
53 struct drm_i915_gem_execbuffer2 execbuf;
54 struct drm_i915_gem_exec_object2 gem_exec[1];
55 struct drm_i915_gem_relocation_entry gem_reloc[1];
57 gem_reloc[0].offset = 1024;
58 gem_reloc[0].delta = 0;
59 gem_reloc[0].target_handle = handle;
60 gem_reloc[0].read_domains = I915_GEM_DOMAIN_RENDER;
61 gem_reloc[0].write_domain = 0;
62 gem_reloc[0].presumed_offset = 0;
64 gem_exec[0].handle = handle;
65 gem_exec[0].relocation_count = 1;
66 gem_exec[0].relocs_ptr = (uintptr_t) gem_reloc;
67 gem_exec[0].alignment = 0;
68 gem_exec[0].offset = 0;
69 gem_exec[0].flags = 0;
70 gem_exec[0].rsvd1 = 0;
71 gem_exec[0].rsvd2 = 0;
73 execbuf.buffers_ptr = (uintptr_t)gem_exec;
74 execbuf.buffer_count = 1;
75 execbuf.batch_start_offset = 0;
76 execbuf.batch_len = 8;
77 execbuf.cliprects_ptr = 0;
78 execbuf.num_cliprects = 0;
82 i915_execbuffer2_set_context_id(execbuf, 0);
85 do_or_die(drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf));
86 igt_assert(gem_exec[0].offset == offset);
89 static int gem_linear_blt(int fd,
94 struct drm_i915_gem_relocation_entry *reloc)
98 *b++ = COPY_BLT_CMD | BLT_WRITE_ALPHA | BLT_WRITE_RGB;
99 *b++ = 0x66 << 16 | 1 << 25 | 1 << 24 | (4*1024);
101 *b++ = (length / (4*1024)) << 16 | 1024;
103 reloc->offset = (b-batch-1) * sizeof(uint32_t);
105 reloc->target_handle = dst;
106 reloc->read_domains = I915_GEM_DOMAIN_RENDER;
107 reloc->write_domain = I915_GEM_DOMAIN_RENDER;
108 reloc->presumed_offset = 0;
110 if (intel_gen(intel_get_drm_devid(fd)) >= 8)
111 *b++ = 0; /* FIXME */
116 reloc->offset = (b-batch-1) * sizeof(uint32_t);
118 reloc->target_handle = src;
119 reloc->read_domains = I915_GEM_DOMAIN_RENDER;
120 reloc->write_domain = 0;
121 reloc->presumed_offset = 0;
123 if (intel_gen(intel_get_drm_devid(fd)) >= 8)
124 *b++ = 0; /* FIXME */
126 *b++ = MI_BATCH_BUFFER_END;
129 return (b - batch) * sizeof(uint32_t);
132 static void make_busy(int fd, uint32_t handle)
134 struct drm_i915_gem_execbuffer2 execbuf;
135 struct drm_i915_gem_exec_object2 obj[2];
136 struct drm_i915_gem_relocation_entry reloc[2];
141 tmp = gem_create(fd, 1024*1024);
144 obj[0].relocation_count = 0;
145 obj[0].relocs_ptr = 0;
146 obj[0].alignment = 0;
152 obj[1].handle = handle;
153 obj[1].relocation_count = 2;
154 obj[1].relocs_ptr = (uintptr_t) reloc;
155 obj[1].alignment = 0;
161 execbuf.buffers_ptr = (uintptr_t)obj;
162 execbuf.buffer_count = 2;
163 execbuf.batch_start_offset = 0;
164 execbuf.batch_len = gem_linear_blt(fd, batch, tmp, tmp, 1024*1024,reloc);
165 execbuf.cliprects_ptr = 0;
166 execbuf.num_cliprects = 0;
170 if (HAS_BLT_RING(intel_get_drm_devid(fd)))
171 execbuf.flags |= I915_EXEC_BLT;
172 i915_execbuffer2_set_context_id(execbuf, 0);
175 gem_write(fd, handle, 0, batch, execbuf.batch_len);
176 for (count = 0; count < 10; count++)
177 do_or_die(drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf));
181 static int test_can_pin(int fd)
183 struct drm_i915_gem_pin pin;
186 pin.handle = gem_create(fd, 4096);;
188 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_PIN, &pin);
189 gem_close(fd, pin.handle);
194 static uint32_t gem_pin(int fd, int handle, int alignment)
196 struct drm_i915_gem_pin pin;
199 pin.alignment = alignment;
200 do_ioctl(fd, DRM_IOCTL_I915_GEM_PIN, &pin);
206 const uint32_t batch[2] = {MI_BATCH_BUFFER_END};
207 struct timeval start, now;
208 uint32_t *handle, *offset;
211 igt_skip_on_simulation();
215 igt_require(test_can_pin(fd));
217 handle = malloc(sizeof(uint32_t)*100);
218 offset = malloc(sizeof(uint32_t)*100);
220 /* Race creation/use against interrupts */
221 igt_fork_signal_helper();
222 gettimeofday(&start, NULL);
224 for (i = 0; i < 100; i++) {
227 handle[i] = gem_create(fd, 4096);
228 offset[i] = gem_pin(fd, handle[i], 0);
229 igt_assert(offset[i]);
230 gem_write(fd, handle[i], 0, batch, sizeof(batch));
232 /* try to pin an anidle bo */
233 handle[i] = gem_create(fd, 4096);
234 make_busy(fd, handle[i]);
235 offset[i] = gem_pin(fd, handle[i], 256*1024);
236 igt_assert(offset[i]);
237 igt_assert((offset[i] & (256*1024-1)) == 0);
238 gem_write(fd, handle[i], 0, batch, sizeof(batch));
241 for (i = 0; i < 1000; i++) {
242 int j = rand() % 100;
243 exec(fd, handle[j], offset[j]);
245 for (i = 0; i < 100; i++)
246 gem_close(fd, handle[i]);
247 gettimeofday(&now, NULL);
248 } while ((now.tv_sec - start.tv_sec)*1000 + (now.tv_usec - start.tv_usec) / 1000 < 10000);
249 igt_stop_signal_helper();