tests/gem_partial_pwrite_pread.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Daniel Vetter <daniel.vetter@ffwll.ch>
  25  *
  26  */
  27
  28 #include <stdlib.h>
  29 #include <stdio.h>
  30 #include <string.h>
  31 #include <fcntl.h>
  32 #include <inttypes.h>
  33 #include <errno.h>
  34 #include <sys/stat.h>
  35 #include <sys/time.h>
  36
  37 #include <drm.h>
  38
  39 #include "ioctl_wrappers.h"
  40 #include "drmtest.h"
  41 #include "intel_chipset.h"
  42 #include "intel_io.h"
  43 #include "igt_aux.h"
  44
  45 /*
  46  * Testcase: pwrite/pread consistency when touching partial cachelines
  47  *
  48  * Some fancy new pwrite/pread optimizations clflush in-line while
  49  * reading/writing. Check whether all required clflushes happen.
  50  *
  51  */
  52
  53 static drm_intel_bufmgr *bufmgr;
  54 struct intel_batchbuffer *batch;
  55
  56 drm_intel_bo *scratch_bo;
  57 drm_intel_bo *staging_bo;
  58 #define BO_SIZE (4*4096)
  59 uint32_t devid;
  60 uint64_t mappable_gtt_limit;
  61 int fd;
  62
  63 static void
  64 copy_bo(drm_intel_bo *src, drm_intel_bo *dst)
  65 {
  66         BLIT_COPY_BATCH_START(devid, 0);
  67         OUT_BATCH((3 << 24) | /* 32 bits */
  68                   (0xcc << 16) | /* copy ROP */
  69                   4096);
  70         OUT_BATCH(0 << 16 | 0);
  71         OUT_BATCH((BO_SIZE/4096) << 16 | 1024);
  72         OUT_RELOC_FENCED(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
  73         OUT_BATCH(0 << 16 | 0);
  74         OUT_BATCH(4096);
  75         OUT_RELOC_FENCED(src, I915_GEM_DOMAIN_RENDER, 0, 0);
  76         ADVANCE_BATCH();
  77
  78         intel_batchbuffer_flush(batch);
  79 }
  80
  81 static void
  82 blt_bo_fill(drm_intel_bo *tmp_bo, drm_intel_bo *bo, int val)
  83 {
  84         uint8_t *gtt_ptr;
  85         int i;
  86
  87         drm_intel_gem_bo_map_gtt(tmp_bo);
  88         gtt_ptr = tmp_bo->virtual;
  89
  90         for (i = 0; i < BO_SIZE; i++)
  91                 gtt_ptr[i] = val;
  92
  93         drm_intel_gem_bo_unmap_gtt(tmp_bo);
  94
  95         if (bo->offset < mappable_gtt_limit &&
  96             (IS_G33(devid) || intel_gen(devid) >= 4))
  97                 igt_trash_aperture();
  98
  99         copy_bo(tmp_bo, bo);
 100 }
 101
 102 #define MAX_BLT_SIZE 128
 103 #define ROUNDS 1000
 104 uint8_t tmp[BO_SIZE];
 105
 106 static void test_partial_reads(void)
 107 {
 108         int i, j;
 109
 110         igt_info("checking partial reads\n");
 111         for (i = 0; i < ROUNDS; i++) {
 112                 int start, len;
 113                 int val = i % 256;
 114
 115                 blt_bo_fill(staging_bo, scratch_bo, i);
 116
 117                 start = random() % BO_SIZE;
 118                 len = random() % (BO_SIZE-start) + 1;
 119
 120                 drm_intel_bo_get_subdata(scratch_bo, start, len, tmp);
 121                 for (j = 0; j < len; j++) {
 122                         igt_assert_f(tmp[j] == val,
 123                                      "mismatch at %i, got: %i, expected: %i\n",
 124                                      j, tmp[j], val);
 125                 }
 126
 127                 igt_progress("partial reads test: ", i, ROUNDS);
 128         }
 129
 130 }
 131
 132 static void test_partial_writes(void)
 133 {
 134         int i, j;
 135         uint8_t *gtt_ptr;
 136
 137         igt_info("checking partial writes\n");
 138         for (i = 0; i < ROUNDS; i++) {
 139                 int start, len;
 140                 int val = i % 256;
 141
 142                 blt_bo_fill(staging_bo, scratch_bo, i);
 143
 144                 start = random() % BO_SIZE;
 145                 len = random() % (BO_SIZE-start) + 1;
 146
 147                 memset(tmp, i + 63, BO_SIZE);
 148
 149                 drm_intel_bo_subdata(scratch_bo, start, len, tmp);
 150
 151                 copy_bo(scratch_bo, staging_bo);
 152                 drm_intel_gem_bo_map_gtt(staging_bo);
 153                 gtt_ptr = staging_bo->virtual;
 154
 155                 for (j = 0; j < start; j++) {
 156                         igt_assert_f(gtt_ptr[j] == val,
 157                                      "mismatch at %i, got: %i, expected: %i\n",
 158                                      j, tmp[j], val);
 159                 }
 160                 for (; j < start + len; j++) {
 161                         igt_assert_f(gtt_ptr[j] == tmp[0],
 162                                      "mismatch at %i, got: %i, expected: %i\n",
 163                                      j, tmp[j], i);
 164                 }
 165                 for (; j < BO_SIZE; j++) {
 166                         igt_assert_f(gtt_ptr[j] == val,
 167                                      "mismatch at %i, got: %i, expected: %i\n",
 168                                      j, tmp[j], val);
 169                 }
 170                 drm_intel_gem_bo_unmap_gtt(staging_bo);
 171
 172                 igt_progress("partial writes test: ", i, ROUNDS);
 173         }
 174
 175 }
 176
 177 static void test_partial_read_writes(void)
 178 {
 179         int i, j;
 180         uint8_t *gtt_ptr;
 181
 182         igt_info("checking partial writes after partial reads\n");
 183         for (i = 0; i < ROUNDS; i++) {
 184                 int start, len;
 185                 int val = i % 256;
 186
 187                 blt_bo_fill(staging_bo, scratch_bo, i);
 188
 189                 /* partial read */
 190                 start = random() % BO_SIZE;
 191                 len = random() % (BO_SIZE-start) + 1;
 192
 193                 drm_intel_bo_get_subdata(scratch_bo, start, len, tmp);
 194                 for (j = 0; j < len; j++) {
 195                         igt_assert_f(tmp[j] == val,
 196                                      "mismatch in read at %i, got: %i, expected: %i\n",
 197                                      j, tmp[j], val);
 198                 }
 199
 200                 /* Change contents through gtt to make the pread cachelines
 201                  * stale. */
 202                 val = (i + 17) % 256;
 203                 blt_bo_fill(staging_bo, scratch_bo, val);
 204
 205                 /* partial write */
 206                 start = random() % BO_SIZE;
 207                 len = random() % (BO_SIZE-start) + 1;
 208
 209                 memset(tmp, i + 63, BO_SIZE);
 210
 211                 drm_intel_bo_subdata(scratch_bo, start, len, tmp);
 212
 213                 copy_bo(scratch_bo, staging_bo);
 214                 drm_intel_gem_bo_map_gtt(staging_bo);
 215                 gtt_ptr = staging_bo->virtual;
 216
 217                 for (j = 0; j < start; j++) {
 218                         igt_assert_f(gtt_ptr[j] == val,
 219                                      "mismatch at %i, got: %i, expected: %i\n",
 220                                      j, tmp[j], val);
 221                 }
 222                 for (; j < start + len; j++) {
 223                         igt_assert_f(gtt_ptr[j] == tmp[0],
 224                                      "mismatch at %i, got: %i, expected: %i\n",
 225                                      j, tmp[j], tmp[0]);
 226                 }
 227                 for (; j < BO_SIZE; j++) {
 228                         igt_assert_f(gtt_ptr[j] == val,
 229                                      "mismatch at %i, got: %i, expected: %i\n",
 230                                      j, tmp[j], val);
 231                 }
 232                 drm_intel_gem_bo_unmap_gtt(staging_bo);
 233
 234                 igt_progress("partial read/writes test: ", i, ROUNDS);
 235         }
 236 }
 237
 238 static void do_tests(int cache_level, const char *suffix)
 239 {
 240         igt_fixture {
 241                 if (cache_level != -1)
 242                         gem_set_caching(fd, scratch_bo->handle, cache_level);
 243         }
 244
 245         igt_subtest_f("reads%s", suffix)
 246                 test_partial_reads();
 247
 248         igt_subtest_f("write%s", suffix)
 249                 test_partial_writes();
 250
 251         igt_subtest_f("writes-after-reads%s", suffix)
 252                 test_partial_read_writes();
 253 }
 254
 255 igt_main
 256 {
 257         srandom(0xdeadbeef);
 258
 259         igt_skip_on_simulation();
 260
 261         igt_fixture {
 262                 fd = drm_open_any();
 263
 264                 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
 265                 //drm_intel_bufmgr_gem_enable_reuse(bufmgr);
 266                 devid = intel_get_drm_devid(fd);
 267                 batch = intel_batchbuffer_alloc(bufmgr, devid);
 268
 269                 /* overallocate the buffers we're actually using because */
 270                 scratch_bo = drm_intel_bo_alloc(bufmgr, "scratch bo", BO_SIZE, 4096);
 271                 staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
 272
 273                 igt_init_aperture_trashers(bufmgr);
 274                 mappable_gtt_limit = gem_mappable_aperture_size();
 275         }
 276
 277         do_tests(-1, "");
 278
 279         /* Repeat the tests using different levels of snooping */
 280         do_tests(0, "-uncached");
 281         do_tests(1, "-snoop");
 282         do_tests(2, "-display");
 283
 284         igt_fixture {
 285                 igt_cleanup_aperture_trashers();
 286                 drm_intel_bufmgr_destroy(bufmgr);
 287
 288                 close(fd);
 289         }
 290 }