2 * Copyright © 2009 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
28 /** @file gem_linear_blits.c
30 * This is a test of doing many blits, with a working set
31 * larger than the aperture size.
33 * The goal is to simply ensure the basics work.
47 #include "ioctl_wrappers.h"
48 #include "intel_chipset.h"
56 static uint32_t linear[WIDTH*HEIGHT];
59 copy(int fd, uint32_t dst, uint32_t src)
62 struct drm_i915_gem_relocation_entry reloc[2];
63 struct drm_i915_gem_exec_object2 obj[3];
64 struct drm_i915_gem_execbuffer2 exec;
68 batch[i++] = XY_SRC_COPY_BLT_CMD |
69 XY_SRC_COPY_BLT_WRITE_ALPHA |
70 XY_SRC_COPY_BLT_WRITE_RGB;
71 if (intel_gen(intel_get_drm_devid(fd)) >= 8)
76 batch[i++] = (3 << 24) | /* 32 bits */
77 (0xcc << 16) | /* copy ROP */
79 batch[i++] = 0; /* dst x1,y1 */
80 batch[i++] = (HEIGHT << 16) | WIDTH; /* dst x2,y2 */
81 batch[i++] = 0; /* dst reloc */
82 if (intel_gen(intel_get_drm_devid(fd)) >= 8)
84 batch[i++] = 0; /* src x1,y1 */
86 batch[i++] = 0; /* src reloc */
87 if (intel_gen(intel_get_drm_devid(fd)) >= 8)
89 batch[i++] = MI_BATCH_BUFFER_END;
92 handle = gem_create(fd, 4096);
93 gem_write(fd, handle, 0, batch, sizeof(batch));
95 reloc[0].target_handle = dst;
97 reloc[0].offset = 4 * sizeof(batch[0]);
98 reloc[0].presumed_offset = 0;
99 reloc[0].read_domains = I915_GEM_DOMAIN_RENDER;;
100 reloc[0].write_domain = I915_GEM_DOMAIN_RENDER;
102 reloc[1].target_handle = src;
104 reloc[1].offset = 7 * sizeof(batch[0]);
105 if (intel_gen(intel_get_drm_devid(fd)) >= 8)
106 reloc[1].offset += sizeof(batch[0]);
107 reloc[1].presumed_offset = 0;
108 reloc[1].read_domains = I915_GEM_DOMAIN_RENDER;;
109 reloc[1].write_domain = 0;
112 obj[0].relocation_count = 0;
113 obj[0].relocs_ptr = 0;
114 obj[0].alignment = 0;
121 obj[1].relocation_count = 0;
122 obj[1].relocs_ptr = 0;
123 obj[1].alignment = 0;
129 obj[2].handle = handle;
130 obj[2].relocation_count = 2;
131 obj[2].relocs_ptr = (uintptr_t)reloc;
132 obj[2].alignment = 0;
135 obj[2].rsvd1 = obj[2].rsvd2 = 0;
137 exec.buffers_ptr = (uintptr_t)obj;
138 exec.buffer_count = 3;
139 exec.batch_start_offset = 0;
140 exec.batch_len = i * 4;
141 exec.DR1 = exec.DR4 = 0;
142 exec.num_cliprects = 0;
143 exec.cliprects_ptr = 0;
144 exec.flags = HAS_BLT_RING(intel_get_drm_devid(fd)) ? I915_EXEC_BLT : 0;
145 i915_execbuffer2_set_context_id(exec, 0);
148 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
149 while (ret && errno == EBUSY) {
150 drmCommandNone(fd, DRM_I915_GEM_THROTTLE);
151 ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
153 igt_assert(ret == 0);
155 gem_close(fd, handle);
159 create_bo(int fd, uint32_t val)
164 handle = gem_create(fd, sizeof(linear));
166 /* Fill the BO with dwords starting at val */
167 for (i = 0; i < WIDTH*HEIGHT; i++)
169 gem_write(fd, handle, 0, linear, sizeof(linear));
175 check_bo(int fd, uint32_t handle, uint32_t val)
179 gem_read(fd, handle, 0, linear, sizeof(linear));
180 for (i = 0; i < WIDTH*HEIGHT; i++) {
181 igt_assert_f(linear[i] == val,
182 "Expected 0x%08x, found 0x%08x "
183 "at offset 0x%08x\n",
184 val, linear[i], i * 4);
189 static void run_test(int fd, int count)
191 uint32_t *handle, *start_val;
195 handle = malloc(sizeof(uint32_t)*count*2);
196 start_val = handle + count;
198 for (i = 0; i < count; i++) {
199 handle[i] = create_bo(fd, start);
200 start_val[i] = start;
201 start += 1024 * 1024 / 4;
204 igt_info("Verifying initialisation...\n");
205 for (i = 0; i < count; i++)
206 check_bo(fd, handle[i], start_val[i]);
208 igt_info("Cyclic blits, forward...\n");
209 for (i = 0; i < count * 4; i++) {
211 int dst = (i + 1) % count;
213 copy(fd, handle[dst], handle[src]);
214 start_val[dst] = start_val[src];
216 for (i = 0; i < count; i++)
217 check_bo(fd, handle[i], start_val[i]);
219 igt_info("Cyclic blits, backward...\n");
220 for (i = 0; i < count * 4; i++) {
221 int src = (i + 1) % count;
224 copy(fd, handle[dst], handle[src]);
225 start_val[dst] = start_val[src];
227 for (i = 0; i < count; i++)
228 check_bo(fd, handle[i], start_val[i]);
230 igt_info("Random blits...\n");
231 for (i = 0; i < count * 4; i++) {
232 int src = random() % count;
233 int dst = random() % count;
238 copy(fd, handle[dst], handle[src]);
239 start_val[dst] = start_val[src];
241 for (i = 0; i < count; i++) {
242 check_bo(fd, handle[i], start_val[i]);
243 gem_close(fd, handle[i]);
249 int main(int argc, char **argv)
251 int fd = 0, count = 0;
253 igt_skip_on_simulation();
255 igt_subtest_init(argc, argv);
261 count = atoi(argv[1]);
263 count = 3 * gem_aperture_size(fd) / (1024*1024) / 2;
264 else if (count < 2) {
265 fprintf(stderr, "count must be >= 2\n");
269 if (count > intel_get_total_ram_mb() * 9 / 10) {
270 count = intel_get_total_ram_mb() * 9 / 10;
271 igt_info("not enough RAM to run test, reducing buffer count\n");
274 igt_info("Using %d 1MiB buffers\n", count);
277 igt_subtest("normal")
280 igt_subtest("interruptible") {
281 igt_fork_signal_helper();
283 igt_stop_signal_helper();