2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Vetter <daniel.vetter@ffwll.ch>
37 #include "ioctl_wrappers.h"
39 #include "intel_bufmgr.h"
40 #include "intel_batchbuffer.h"
42 #include "intel_chipset.h"
45 * Testcase: Provoke the hangcheck timer on an otherwise idle system
47 * This tries to hit forcewake locking bugs when the hangcheck runs. Somehow we
48 * often luck out and the hangcheck runs while someone else is already holding
49 * the dev->struct_mutex.
51 * It's imperative that nothing else runs while this test runs, i.e. kill your X
55 static drm_intel_bufmgr *bufmgr;
56 struct intel_batchbuffer *batch;
58 uint32_t blob[2048*2048];
60 #define MAX_BLT_SIZE 128
63 drm_intel_bo *bo = NULL;
64 uint32_t tiling_mode = I915_TILING_X;
65 unsigned long pitch, act_size;
68 igt_skip_on_simulation();
70 memset(blob, 'A', sizeof(blob));
74 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
75 drm_intel_bufmgr_gem_enable_reuse(bufmgr);
76 devid = intel_get_drm_devid(fd);
77 batch = intel_batchbuffer_alloc(bufmgr, devid);
80 igt_info("filling ring\n");
81 drm_intel_bo_unreference(bo);
82 bo = drm_intel_bo_alloc_tiled(bufmgr, "tiled bo", act_size, act_size,
83 4, &tiling_mode, &pitch, 0);
85 drm_intel_bo_subdata(bo, 0, act_size*act_size*4, blob);
90 for (i = 0; i < 10000; i++) {
91 BLIT_COPY_BATCH_START(devid,
92 XY_SRC_COPY_BLT_SRC_TILED |
93 XY_SRC_COPY_BLT_DST_TILED);
94 OUT_BATCH((3 << 24) | /* 32 bits */
95 (0xcc << 16) | /* copy ROP */
97 OUT_BATCH(0 << 16 | 1024);
98 OUT_BATCH((2048) << 16 | (2048));
99 OUT_RELOC_FENCED(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
100 BLIT_RELOC_UDW(devid);
101 OUT_BATCH(0 << 16 | 0);
103 OUT_RELOC_FENCED(bo, I915_GEM_DOMAIN_RENDER, 0, 0);
104 BLIT_RELOC_UDW(devid);
107 if (IS_GEN6(devid) || IS_GEN7(devid)) {
109 OUT_BATCH(XY_SETUP_CLIP_BLT_CMD);
116 igt_info("waiting\n");
119 igt_info("done waiting, check dmesg\n");
120 drm_intel_bo_unreference(bo);
122 intel_batchbuffer_free(batch);
123 drm_intel_bufmgr_destroy(bufmgr);